Duarte Lopes de Oliveira
According to our database1,
Duarte Lopes de Oliveira
authored at least 37 papers
between 2000 and 2023.
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Bibliography
2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
2022
Fault-Tolerant Finite State Machine Quasi Delay Insensitive in Commercial FPGA Devices.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
2021
A novel approach for the design of low-power pipelined synchronous systems operating in double-edge of the clock.
Microelectron. J., 2021
Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
New Low-Power Architectures of Support Vector Machine Classifier for Speech Recognition System.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
2020
A low-power asynchronous hardware implementation of a novel SVM classifier, with an application in a speech recognition system.
Microelectron. J., 2020
Implementation of Asynchronous Pipelines with QDI Template onto FPGAs Using Commercial Tools.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
2019
Multim. Tools Appl., 2019
Implementation of DES Algorithm in New Non-Synchronous Architecture Aiming DPA Robustness.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
An Implementation of Extended Burst-Mode Specifications as Quasi Delay Insensitive State Machines.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
A Tools Flow for Synthesis of Asynchronous Control Circuits from Extended STG Specifications.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
A State Assignment Method for Extended Burst-Mode gC Finite State Machines Based on Genetic Algorithm.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
2018
A novel fully-programmable analog fuzzifier architecture for interval type-2 fuzzy controllers using current steering mirrors.
J. Intell. Fuzzy Syst., 2018
A Novel Tool for Synthesis by Direct Mapping of Asynchronous Circuits from Extended STG Specifications.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
A novel state assignment method for XBM AFSMs without the essential hazard assumption.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
A design flow of asynchronous burst-mode circuits without fundamental-mode timing assumption.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
2017
Implementation of Locally-Clocked XBM State Machines on FPGAs Using Synchronous CAD Tools.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
2016
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
A design flow for locally-clocked XBM asynchronous state machines using synchronous CAD tools.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
2015
Minimization and Encoding of High Performance Asynchronous State Machines Based on Genetic Algorithm.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
A novel asynchronous interface with pausible clock for partitioned synchronous modules.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
2014
A novel State Assignment method for Extended Burst-Mode FSM design using Genetic Algorithm.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
2013
Design of asynchronous systems on FPGA using direct mapping and synchronous specification.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013
Design of synchronous pipeline digital systems operating in double-edge of the clock.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
Design of locally-clocked asynchronous finite state machines using synchronous CAD tools.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
2008
2005
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
2003
Microelectron. Reliab., 2003
2001
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001
2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000