Dragomir Milojevic
Orcid: 0000-0001-5915-5160
According to our database1,
Dragomir Milojevic
authored at least 53 papers
between 2005 and 2024.
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Bibliography
2024
IEEE Trans. Very Large Scale Integr. Syst., November, 2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2024
Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
Microelectron. J., September, 2023
Proceedings of the IEEE International 3D Systems Integration Conference, 2023
2022
Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper.
Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
Proceedings of the GECCO '22: Genetic and Evolutionary Computation Conference, Companion Volume, Boston, Massachusetts, USA, July 9, 2022
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Microprocess. Microsystems, 2021
Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited).
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021
Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
2020
IEEE Comput. Archit. Lett., 2020
2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
2018
Template architectures for highly scalable, many-core Heterogeneous SoC: Could-of-Chips.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018
2017
IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
2016
Exploring Energy Reduction in Future Technology Nodes via Voltage Scaling with Application to 10nm.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers.
Microprocess. Microsystems, 2015
2014
System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform.
IEEE Embed. Syst. Lett., 2014
A context aware cache controller to bridge the gap between theory and practice in real-time systems.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014
2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 24th Euromicro Conference on Real-Time Systems, 2012
Proceedings of the 24th Euromicro Conference on Real-Time Systems, 2012
2011
J. Signal Process. Syst., 2011
Reducing Preemptions and Migrations in Real-Time Multiprocessor Scheduling Algorithms by Releasing the Fairness.
Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011
An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations.
Proceedings of the Design, Automation and Test in Europe, 2011
DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Proceedings of the ARCS '10, 2010
2009
Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications.
J. Signal Process. Syst., 2009
Implementation of the W-CDMA cell search on a MPSOC designed for software defined radios.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management.
Proceedings of the Embedded Computer Systems: Architectures, 2009
Pathfinding: A design methodology for fast exploration and optimisation of 3D-stacked integrated circuits.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study.
Proceedings of the IEEE International Conference on 3D System Integration, 2009
2008
Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip.
IEEE Trans. Computers, 2008
EURASIP J. Embed. Syst., 2008
Proceedings of the IEEE International Conference on Sensor Networks, 2008
Proceedings of the Embedded Computer Systems: Architectures, 2008
Proceedings of the Principles of Distributed Systems, 12th International Conference, 2008
2007
Proceedings of the Embedded Computer Systems: Architectures, 2007
2005
Implementation of Ranking Filters on General Purpose and Reconfigurable Architecture Based on High Density FPGA Devices.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005