Doru-Florin Chiper
Orcid: 0000-0002-3322-4663
According to our database1,
Doru-Florin Chiper
authored at least 24 papers
between 1997 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
Analytic Design Technique for 2D FIR Circular Filter Banks and Their Efficient Implementation Using Polyphase Approach.
Sensors, December, 2023
x-DTT: A package for calculating real and Integer Discrete Tchebichef Transform kernels based on orthogonal polynomials.
SoftwareX, July, 2023
Sensors, July, 2023
Proceedings of the 15th International Conference on Electronics, 2023
2022
An Improved Algorithm for the VLSI Implementation of Type II Generalized DHT that Allows an Efficient Incorporation of Obfuscation Technique.
Proceedings of the 45th International Conference on Telecommunications and Signal Processing, 2022
A New Integer Algorithm for a VLSI Implementation of DCT Using Obfuscation Technique.
Proceedings of the 14th International Conference on Communications, 2022
An Improved Algorithm for an Efficient VLSI Implementation of Type IV DST using Short Quasi-Band Correlation Structures.
Proceedings of the 14th International Conference on Electronics, 2022
2021
A Structured Fast Algorithm for the VLSI Pipeline Implementation of Inverse Discrete Cosine Transform.
Circuits Syst. Signal Process., 2021
2020
A New VLSI Algorithm for type IV DCT for an Efficient Implementation of Obfuscation Technique.
Proceedings of the 43rd International Conference on Telecommunications and Signal Processing, 2020
A New VLSI Algorithm for an Efficient VLSI Implementation of Type IV DST based on Short Band- Correlation Structures.
Proceedings of the 13th International Conference on Communications, 2020
2018
A Structured Dual Split-Radix Algorithm for the Discrete Hartley Transform of Length \(2^{N}\).
Circuits Syst. Signal Process., 2018
Proceedings of the 2018 10th International Conference on Electronics, 2018
2016
Proceedings of the International Conference on Communications, 2016
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
2011
IEEE Signal Process. Lett., 2011
Novel VLSI Algorithm and Architecture with Good Quantization Properties for a High-Throughput Area Efficient Systolic Array Implementation of DCT.
EURASIP J. Adv. Signal Process., 2011
A new VLSI algorithm and architecture for the hardware implementation of type IV discrete cosine transform using a pseudo-band correlation structure.
Central Eur. J. Comput. Sci., 2011
2008
A new systolic array algorithm for a high throughput low cost VLSI implementation of DCT.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
An Efficient Unified Framework for Implementation of a Prime-Length DCT/IDCT With High Throughput.
IEEE Trans. Signal Process., 2007
2005
Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
2002
IEEE Trans. Signal Process., 2002
1999
A Systolic Array Algorithm for an Efficient Unified Memory-Based Implementation of the Inverse Discrete Cosine and Sine Transforms.
Proceedings of the 1999 International Conference on Image Processing, 1999
1997
Proceedings of the Second IEEE Symposium on Computers and Communications (ISCC 1997), 1997