Doron Drusinsky

Computer, April, 2024

Discovering Decision Manifolds to Assure Trusted Autonomous Systems.

[BibT_eX]

[DOI]

CoRR, 2024

2023

Machine-Learned Verification and Advance Notice Oracles for Autonomous Systems.

[BibT_eX]

[DOI]

Computer, 2023

Encrypting for Time- and/or Location-Based Decryption.

[BibT_eX]

[DOI]

Computer, 2023

2022

Lightweight Verification and Validation of Cyberphysical Systems Using Machine-Learned Correctness Properties.

[BibT_eX]

[DOI]

Computer, 2022

On the High-Energy Consumption of Bitcoin Mining.

[BibT_eX]

[DOI]

Computer, 2022

Cryptographic-Biometric Self-Sovereign Personal Identities.

[BibT_eX]

[DOI]

Computer, 2022

Machine-Learned Specifications for the Verification and Validation of Autonomous Cyberphysical Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Software Reliability Engineering Workshops, 2022

2021

Formal Methods in Cyberphysical Systems.

[BibT_eX]

[DOI]

Duminda Wijesekera

Computer, 2021

Formal Verification of Cyberphysical Systems.

[BibT_eX]

[DOI]

Duminda Wijesekera

Computer, 2021

Multiagent Pathfinding Under Rigid, Optimization, and Uncertainty Constraints.

[BibT_eX]

[DOI]

Computer, 2021

Who Is Authenticating My E-Commerce Logins?

[BibT_eX]

[DOI]

Computer, 2021

2020

Open Questions in Formal Methods.

[BibT_eX]

[DOI]

George W. Dinolt

Computer, 2020

Obtaining Trust in Executable Derivatives Using Crowdsourced Critiques With Blind Signatures.

[BibT_eX]

[DOI]

Computer, 2020

2017

Reverse engineering concurrent UML state machines using black box testing and genetic programming.

[BibT_eX]

[DOI]

Innov. Syst. Softw. Eng., 2017

Online, library-based visual formal specification monitoring system for monitoring log-files with visible and hidden data.

[BibT_eX]

[DOI]

Innov. Syst. Softw. Eng., 2017

2016

Run-time monitoring using bounded constraint instance discovery within big data streams.

[BibT_eX]

[DOI]

Innov. Syst. Softw. Eng., 2016

2015

Early detection of evolving system failures and temporal conflicts using parameterized formal specifications and bounded constraint-solving.

[BibT_eX]

[DOI]

Innov. Syst. Softw. Eng., 2015

2014

Modeling Human-in-the-Loop Security Analysis and Decision-Making Processes.

[BibT_eX]

[DOI]

IEEE Trans. Software Eng., 2014

Computer-aided discovery of formal specification behavioral requirements and requirement to implementation mappings.

[BibT_eX]

[DOI]

Innov. Syst. Softw. Eng., 2014

Runtime monitoring and verification of systems with hidden information.

[BibT_eX]

[DOI]

Innov. Syst. Softw. Eng., 2014

2013

End-to-End Formal Specification, Validation, and Verification Process: A Case Study of Space Flight Software.

[BibT_eX]

[DOI]

Miriam C. Bergue Alves

IEEE Syst. J., 2013

Behavioral and Temporal Rule Checking for Gaussian Random Process - a Kalman Filter Example.

[BibT_eX]

[DOI]

J. Univers. Comput. Sci., 2013

2012

Validating quality attribute requirements via execution-based model checking.

[BibT_eX]

[DOI]

Softw. Pract. Exp., 2012

Behavioral and Temporal Pattern Detection within Financial Data with Hidden Information.

[BibT_eX]

[DOI]

J. Univers. Comput. Sci., 2012

Runtime Verification of Systems with Hidden Information.

[BibT_eX]

[DOI]

Proceedings of the Infotech@Aerospace 2012, 2012

2011

Verification and Validation for Trustworthy Software Systems.

[BibT_eX]

[DOI]

IEEE Softw., 2011

Rapid runtime system verification using automatic source code instrumentation.

[BibT_eX]

[DOI]

J. Bret Michael

Proceedings of the 6th International Conference on System of Systems Engineering, 2011

Putting order into the cloud: Object-oriented UML-based enforcement for document and application organization.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on System of Systems Engineering, 2011

Formal validation and verification of space flight software using statechart-assertions and runtime execution monitoring.

[BibT_eX]

[DOI]

Miriam C. Bergue Alves

J. Bret Michael

Proceedings of the 6th International Conference on System of Systems Engineering, 2011

2010

Removing the Boundaries: Steps Toward a Cloud Nirvana.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE International Conference on Granular Computing, 2010

2009

TLtoSQL: Rapid post-mortem verification using temporal logic to SQL code generation in the Eclipse PDE.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on System of Systems Engineering, 2009

Guarding the guard: Using meta formal specifications to guard assertions.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on System of Systems Engineering, 2009

Using UML Statecharts with Knowledge Logic Guards.

[BibT_eX]

[DOI]

Proceedings of the Model Driven Engineering Languages and Systems, 2009

2008

A Visual Tradeoff Space for Formal Verification and Validation Techniques.

[BibT_eX]

[DOI]

IEEE Syst. J., 2008

A framework for computer-aided validation.

[BibT_eX]

[DOI]

Innov. Syst. Softw. Eng., 2008

Integrating statechart assertions into Java components using AspectJ.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on System of Systems Engineering, 2008

From UML activity diagrams to specification requirements.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on System of Systems Engineering, 2008

Validating UML Statechart-Based Assertions Libraries for Improved Reliability and Assurance.

[BibT_eX]

[DOI]

Proceedings of the Second International Conference on Secure System Integration and Reliability Improvement, 2008

2007

Creating and Validating Embedded Assertion Statecharts.

[BibT_eX]

[DOI]

Kadir Alpaslan Demir

IEEE Distributed Syst. Online, 2007

Specification, Validation and Run-time Monitoring of SOA Based System-of-Systems Temporal Behaviors.

[BibT_eX]

[DOI]

Thomas S. Cook

Proceedings of the 2nd IEEE International Conference on System of Systems Engineering, 2007

Verifying Distributed Protocols using MSC-Assertions, Run-time Monitoring, and Automatic Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

A design pattern for using non-developmental items in real-time Java.

[BibT_eX]

[DOI]

Proceedings of the 5th International Workshop on Java Technologies for Real-time and Embedded Systems, 2007

2006

On-line Monitoring of Metric Temporal Logic with Time-Series Constraints Using Alternating Finite Automata.

[BibT_eX]

[DOI]

J. Univers. Comput. Sci., 2006

Quality assurance of the timing properties of real-time, reactive system-of-systems.

[BibT_eX]

[DOI]

Thomas S. Cook

Proceedings of the 1st IEEE/SMC International Conference on System of Systems Engineering, 2006

Creation and Validation of Embedded Assertion Statecharts.

[BibT_eX]

[DOI]

Kadir Alpaslan Demir

Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

Modeling and verification using UML statecharts - a working guide to reactive system design, runtime monitoring and execution-based model checking.

[BibT_eX]

Elsevier, ISBN: 978-0-7506-7949-7, 2006

2005

Creation and evaluation of formal specifications for system-of-systems development.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Systems, 2005

Test-Time, Run-Time, and Simulation-Time Temporal Assertions in RSP.

[BibT_eX]

[DOI]

Kadir Alpaslan Demir

Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Architectural Design, Behavior Modeling and Run-Time Verification of Network Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Reliable Systems on Unreliable Networked Platforms, 2005

2004

Experimental Evaluation of Verification and Validation Tools on Martian Rover Software.

[BibT_eX]

[DOI]

Guillaume P. Brat

Dimitra Giannakopoulou

Formal Methods Syst. Des., 2004

Semantics and Runtime Monitoring of TLCharts: Statechart Automata with Temporal Logic Conditioned Transitions.

[BibT_eX]

[DOI]

Proceedings of the Fourth Workshop on Runtime Verification, 2004

TLCharts: Armor-plating Harel Statecharts with Temporal Logic Conditions.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004

Automatic Simulation of Network Problems in UDP-Based Java Programs Temporal Logic and Natural Language Conditioned Transitions.

[BibT_eX]

[DOI]

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003

Monitoring Temporal Logic Specifications Combined with Time Series Constraints.

[BibT_eX]

[DOI]

J. Univers. Comput. Sci., 2003

Applying Run-Time Monitoring to the Deep-Impact Fault Protection Engine.

[BibT_eX]

[DOI]

Garth Watney

Proceedings of the 28th Annual IEEE / NASA Software Engineering Workshop (SEW-28 2003), 2003

Verification of Timing Properties in Rapid System Prototyping.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

Monitoring Temporal Rules Combined with Time Series.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 15th International Conference, 2003

Experiments with Test Case Generation and Runtime Analysis.

[BibT_eX]

[DOI]

Proceedings of the Abstract State Machines, 2003

2000

The Temporal Rover and the ATG Rover.

[BibT_eX]

[DOI]

Proceedings of the SPIN Model Checking and Software Verification, 7th International SPIN Workshop, Stanford, CA, USA, August 30, 2000

1994

On the Power of Bounded Concurrency I: Finite Automata.

[BibT_eX]

[DOI]

David Harel

J. ACM, 1994

1991

Decision problems for interacting finite state machines.

[BibT_eX]

[DOI]

Doron Drusinsky-Yoresh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

A state assignment procedure for single-block implementation of state charts.

[BibT_eX]

[DOI]

Doron Drusinsky-Yoresh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

1990

Symbolic cover minimization of fully I/O specified finite state machines.

[BibT_eX]

[DOI]

Doron Drusinsky-Yoresh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

1989

Using statecharts for hardware description and synthesis.

[BibT_eX]

[DOI]

David Harel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988

On the Power of Cooperative Concurrency.

[BibT_eX]

[DOI]