Dongyun Kam

Orcid: 0000-0002-8542-1845

According to our database¹, Dongyun Kam authored at least 18 papers between 2019 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

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On csauthors.net:

Bibliography

2024

A Design Framework for Cost-Efficient Sorters With Arbitrary Input/Output Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

Hard-Decision SCL Polar Decoder With Weighted Pruning Operation for Storage Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, September, 2024

Panacea: Novel DNN Accelerator using Accuracy-Preserving Asymmetric Quantization and Energy-Saving Bit-Slice Sparsity.

[BibT_eX]

[DOI]

CoRR, 2024

2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

Constrained Sorter Design using Zero-One Principle.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning Operations.

[BibT_eX]

[DOI]

Dongyun Kam

Byeong Yong Kong

Youngjoo Lee

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023

Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022

Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Simplified Ordered Statistic Decoding for Short-Length Linear Block Codes.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2022

A 1.1μs 1.56Gb/s/mm<sup>2</sup> Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology.

[BibT_eX]

[DOI]

Dongyun Kam

Byeong Yong Kong

Youngjoo Lee

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism.

[BibT_eX]

[DOI]

Dongyun Kam

Hoyoung Yoo

Youngjoo Lee

IEEE Trans. Very Large Scale Integr. Syst., 2021

Low-Latency Polar Decoder Using Overlapped SCL Processing.

[BibT_eX]

[DOI]

Dongyun Kam

Byeong Yong Kong

Youngjoo Lee

Proceedings of the IEEE International Conference on Acoustics, 2021

FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020

Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Massive MIMO Systems With Low-Resolution ADCs: Baseband Energy Consumption vs. Symbol Detection Performance.

[BibT_eX]

[DOI]

IEEE Access, 2019

Ultra-Low-Latency Parallel SC Polar Decoding Architecture for 5G Wireless Communications.

[BibT_eX]

[DOI]

Dongyun Kam

Youngjoo Lee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Dongyun Kam

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