Dongyi Liao
Orcid: 0000-0002-2712-7998
According to our database1,
Dongyi Liao
authored at least 8 papers
between 2017 and 2021.
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Bibliography
2021
A Fractional-N Reference Sampling PLL With Linear Sampler and CDAC Based Fractional Spur Cancellation.
IEEE J. Solid State Circuits, 2021
2020
An mm-Wave Synthesizer With Robust Locking Reference-Sampling PLL and Wide-Range Injection-Locked VCO.
IEEE J. Solid State Circuits, 2020
A 7.7~10.3GHz 5.2mW -247.3dB-FOM Fractional-N Reference Sampling PLL with 2nd Order CDAC Based Fractional Spur Cancellation In 45nm CMOS.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
An mm-Wave Synthesizer with Low In-Band Noise and Robust Locking Reference-Sampling PLL.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
IEEE J. Solid State Circuits, 2018
A full-duplex transceiver front-end RFIC with code-domain spread spectrum modulation for Tx self-interference cancellation and in-band jammer rejection.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
An 802.11a/b/g/n Digital Fractional-N PLL With Automatic TDC Linearity Calibration for Spur Cancellation.
IEEE J. Solid State Circuits, 2017
Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust locking.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017