Dongsheng Yang

According to our database, Dongsheng Yang authored at least 13 papers between 2014 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS.

Bangan Liu, Yun Wang, Jian Pang, Haosheng Zhang, Dongsheng Yang, Aravind Tharayil Narayanan, Dae Young Lee, Sung Tae Choi, Rui Wu, Kenichi Okada, Akira Matsuzawa

IEICE Trans. Electron., 2018

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique.

Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang, Hanli Liu, Kenichi Okada, Akira Matsuzawa

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017

A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI.

Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa

IEICE Trans. Electron., 2017

An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation.

Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

A 0.0055mm² 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI.

Dongsheng Yang, Tomohiro Ueno, Wei Deng, Yuki Terashima, Kengo Nakata, Aravind Tharayil Narayanan, Rui Wu, Kenichi Okada, Akira Matsuzawa

IEICE Trans. Electron., 2016

An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB.

Dongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection.

Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique.

Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa

IEEE J. Solid State Circuits, 2015

A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI.

Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Rui Wu, Bangan Liu, Kenichi Okada, Akira Matsuzawa

IEICE Electron. Express, 2015

14.1 A 0.048mm² 3mW synthesizable fractional-N PLL with a soft injection-locking technique.

Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

An HDL-synthesized gated-edge-injection PLL with a current output DAC.

Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

15.1 A 0.0066mm² 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique.

Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 0.011 mm² PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI.

Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014