Dongseok Im
Orcid: 0000-0002-5856-8921
According to our database1,
Dongseok Im
authored at least 37 papers
between 2019 and 2024.
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Bibliography
2024
CamPU: A Multi-Camera Processing Unit for Deep Learning-based 3D Spatial Computing Systems.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024
20.7 NeuGPU: A 18.5mJ/Iter Neural-Graphics Processing Unit for Instant-Modeling and Real-Time Rendering with Segmented-Hashing Architecture.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
20.8 Space-Mate: A 303.5mW Real-Time Sparse Mixture-of-Experts-Based NeRF-SLAM Processor for Mobile Spatial Computing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
LUTein: Dense-Sparse Bit-Slice Architecture With Radix-4 LUT-Based Slice-Tensor Processing Units.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
Space-Mate: A 303.5mW Real-Time NeRF SLAM Processor with Sparse-Mixture-of-Experts-based Acceleration.
Proceedings of the 36th IEEE Hot Chips Symposium, 2024
NeuGPU: A Neural Graphics Processing Unit for Instant Modeling and Real-Time Rendering on Mobile AR/VR Devices.
Proceedings of the 36th IEEE Hot Chips Symposium, 2024
A Low-Power Neural Graphics System for Instant 3D Modeling and Real-Time Rendering on Mobile AR/VR Devices.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2024
A Low-power and Real-time Neural-Rendering Dense SLAM Processor with 3-Level Hierarchical Sparsity Exploitation.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2024
2023
An Efficient Deep-Learning-Based Super-Resolution Accelerating SoC With Heterogeneous Accelerating and Hierarchical Cache.
IEEE J. Solid State Circuits, March, 2023
A Mobile 3-D Object Recognition Processor With Deep-Learning-Based Monocular Depth Estimation.
IEEE Micro, 2023
DSPU: An Efficient Deep Learning-Based Dense RGB-D Data Acquisition With Sensor Fusion and 3-D Perception SoC.
IEEE J. Solid State Circuits, 2023
A 709.3 TOPS/W Event-Driven Smart Vision SoC with High-Linearity and Reconfigurable MRAM PIM.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Sibia: Signed Bit-slice Architecture for Dense DNN Acceleration with Slice-level Sparsity Exploitation.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
A 33.6 FPS Embedding based Real-time Neural Rendering Accelerator with Switchable Computation Skipping Architecture on Edge Device.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A Mobile DNN Training Processor With Automatic Bit Precision Search and Fine-Grained Sparsity Exploitation.
IEEE Micro, 2022
A Pipelined Point Cloud Based Neural Network Processor for 3-D Vision With Large-Scale Max Pooling Layer Prediction.
IEEE J. Solid State Circuits, 2022
CoRR, 2022
DSPU: A 281.6mW Real-Time Depth Signal Processing Unit for Deep Learning-Based Dense RGB-D Data Acquisition with Depth Fusion and 3D Bounding Box Extraction in Mobile Platforms.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
An Efficient High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
DSPU: A 281.6mW Real-Time Deep Learning-Based Dense RGB-D Data Acquisition with Sensor Fusion and 3D Perception System-on-Chip.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
HNPU-V2: A 46.6 FPS DNN Training Processor for Real-World Environmental Adaptation based Robust Object Detection on Mobile Devices.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
A Low-power and Real-time 3D Object Recognition Processor with Dense RGB-D Data Acquisition in Mobile Platforms.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2022
An 0.92 mJ/frame High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
A DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
A 0.95 mJ/frame DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
A 0.82 μW CIS-Based Action Recognition SoC With Self-Adjustable Frame Resolution for Always-on IoT Devices.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
GANPU: An Energy-Efficient Multi-DNN Training Processor for GANs With Speculative Dual-Sparsity Exploitation.
IEEE J. Solid State Circuits, 2021
HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching.
IEEE J. Solid State Circuits, 2021
PNNPU: A 11.9 TOPS/W High-speed 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A 3.6 TOPS/W Hybrid FP-FXP Deep Learning Processor with Outlier Compensation for Image-to-Image Application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
PNNPU: A Fast and Efficient 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
An Energy-Efficient Deep Neural Network Training Processor with Bit-Slice-Level Reconfigurability and Sparsity Exploitation.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2021
2020
A 1.15 TOPS/W Energy-Efficient Capsule Network Accelerator for Real-Time 3D Point Cloud Segmentation in Mobile Environment.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
DT-CNN: An Energy-Efficient Dilated and Transposed Convolutional Neural Network Processor for Region of Interest Based Image Segmentation.
IEEE Trans. Circuits Syst., 2020
A 4.45 ms Low-Latency 3D Point-Cloud-Based Neural Network Processor for Hand Pose Estimation in Immersive Wearable Devices.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
7.4 GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
DT-CNN: Dilated and Transposed Convolution Neural Network Accelerator for Real-Time Image Segmentation on Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019