Dongkook Park

According to our database1, Dongkook Park authored at least 14 papers between 2005 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2014
MoDe-X: Microarchitecture of a Layout-Aware Modular Decoupled Crossbar for On-Chip Interconnects.
IEEE Trans. Computers, 2014

2010
On the Effects of Process Variation in Network-on-Chip Architectures.
IEEE Trans. Dependable Secur. Comput., 2010

FPGA-based prototyping of a 2D MESH / TORUS on-chip interconnect (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2008
MIRA: A Multi-layered On-Chip Interconnect Router Architecture.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Performance and power optimization through data compression in Network-on-Chip architectures.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007
A novel dimensionally-decomposed router for on-chip communication in 3D architectures.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects.
Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects, 2007

2006
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Exploring Fault-Tolerant Network-on-Chip Architectures.
Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN 2006), 2006

2005
A low latency router supporting adaptivity for on-chip interconnects.
Proceedings of the 42nd Design Automation Conference, 2005

Design and analysis of an NoC architecture from performance, reliability and energy perspective.
Proceedings of the 2005 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2005


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