Dongjun Park

Orcid: 0009-0007-1795-7908

According to our database1, Dongjun Park authored at least 14 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
Cloning Hardware Wallet Without Valid Credentials Through Side-Channel Analysis of Hash Function.
IEEE Access, 2024

A $94\text{fs}_{\text{rms}}$-Jitter and -249.3dB FoM 4.0GHz Ring-Oscillator-Based MDLL with Background Calibration of Phase Offset and Injection Slope Mismatch.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023
Stealing Keys From Hardware Wallets: A Single Trace Side-Channel Attack on Elliptic Curve Scalar Multiplication Without Profiling.
IEEE Access, 2023

Autoscaled-Wavelet Convolutional Layer for Deep Learning-Based Side-Channel Analysis.
IEEE Access, 2023

2021
Single trace side-channel attack on key reconciliation in quantum key distribution system and its efficient countermeasures.
ICT Express, 2021

Structured Pattern Pruning Using Regularization.
CoRR, 2021

Workspace Derivation of Arthroscope Using Morphological Data and Standard Portal Placement Method for Shoulder Arthroscopy.
IEEE Access, 2021

Side Channel Vulnerability in Parity Computation of Generic Key Reconciliation Process on QKD.
Proceedings of the International Conference on Information and Communication Technology Convergence, 2021

2020
A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication.
IEICE Electron. Express, 2020

A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL.
Circuits Syst. Signal Process., 2020

Single Trace Attack on Key Reconciliation Process for Quantum Key Distribution.
Proceedings of the International Conference on Information and Communication Technology Convergence, 2020

2018
A 7-GHz Fast-Lock 2-Step TDC-based All-Digital DLL for Post-DDR4 SDRAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A 0.15 to 2.2 GHz all-digital delay-locked loop.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A low-power SerDes for high-speed on-chip networks.
Proceedings of the International SoC Design Conference, 2017


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