Dongju Li

According to our database1, Dongju Li authored at least 55 papers between 1995 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
High Precision Fingerprint Verification for Small Area Sensor Based on Deep Learning.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., January, 2024

A Low-Power Reconfigurable DNN Accelerator for Instruction-Extended RISC-V.
IPSJ Trans. Syst. LSI Des. Methodol., 2024

Energy-Efficient Implementation of YOLOv8, Instance Segmentation, and Pose Detection on RISC-V SoC.
IEEE Access, 2024

2023
Text-Independent Speaker Recognition System Using Feature-Level Fusion for Audio Databases of Various Sizes.
SN Comput. Sci., September, 2023

2019
Speaker Recognition Using LPC, MFCC, ZCR Features with ANN and SVM Classifier for Large Input Database.
Proceedings of the IEEE 4th International Conference on Computer and Communication Systems, 2019

2017
An Accurate and Fast Trace-aware Performance Estimation Model For Prioritized MPSoC Bus With Multiple Interfering Bus-Masters.
IPSJ Trans. Syst. LSI Des. Methodol., 2017

HOG-Based Object Detection Processor Design Using ASIP Methodology.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Narrow Fingerprint Template Synthesis by Clustering Minutiae Descriptors.
IEICE Trans. Inf. Syst., 2017

Hybrid Minutiae Descriptor for Narrow Fingerprint Verification.
IEICE Trans. Inf. Syst., 2017

2016
A Fast Trace Aware Statistical Based Prediction Model with Burst Traffic Modeling for Contention Stall in A Priority Based MPSoC Bus.
IPSJ Trans. Syst. LSI Des. Methodol., 2016

An efficient embedded processor for object detection using ASIP methodology.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
Dalvik Bytecode Acceleration Using Fetch/Decode Hardware Extension.
J. Inf. Process., 2015

Efficient Design Exploration Framework of SW/HW Systems Based on Tightly-coupled Thread Model.
IPSJ Trans. Syst. LSI Des. Methodol., 2015

Register-Based Process Virtual Machine Acceleration Using Hardware Extension with Hybrid Execution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Online Detection of Spoof Fingers for Smartphone-Based Applications.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2014
A Method of Software Development Tool and Hardware Generation for ASIP with a Co-processor based on the Derivative ASIP Approach.
J. Inf. Process., 2014

Retargeting Derivative-ASIP with Assembly Converter Tool.
IEICE Trans. Inf. Syst., 2014

Distributed synchronization for message-passing based embedded multiprocessors.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

Dalvik bytecode acceleration using Fetch/Decode Hardware Extension with hybrid Execution.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Custom instruction search for application specific instruction-set processor using guided simulated annealing.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Flexible and High Performance ASIPs for Pixel Level Image Processing and Two Dimensional Image Processing.
J. Inf. Process., 2013

A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

2012
Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology.
IPSJ Trans. Syst. LSI Des. Methodol., 2012

A Low-Cost and Energy-Efficient Multiprocessor System-on-Chip for UWB MAC Layer.
IEICE Trans. Inf. Syst., 2012

Narrow Fingerprint Sensor Verification with Template Updating Technique.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

A High Level Design of Reconfigurable and High-Performance ASIP Engine for Image Signal Processing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Application-specific Instruction-Set Processor design methodology for wireless image transmission systems.
Proceedings of the International SoC Design Conference, 2012

Robust Multiple Minutiae Partitions for Fingerprint Authentication.
Proceedings of the 2012 International Symposium on Biometrics and Security Technologies, 2012

A Reconfigurable High Performance ASIP Engine for Image Signal Processing.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

A reconfigurable ASIP-based approach for high performance image signal processing.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Unique Fingerprint-Image-Generation Algorithm for Line Sensors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Practical Orientation Field Estimation for Embedded Fingerprint Recognition Systems.
IEICE Trans. Inf. Syst., 2011

2010
A Unified Performance Estimation Method for Hardware and Software Components in Multiprocessor System-On-Chips.
IPSJ Trans. Syst. LSI Des. Methodol., 2010

Orientation Field Estimation for Embedded Fingerprint Authentication System.
IEICE Trans. Inf. Syst., 2010

Ultra fast fingerprint indexing for embedded system.
Proceedings of the Second International Conference of Soft Computing and Pattern Recognition, 2010

A novel similarity measurement for minutiae-based fingerprint verification.
Proceedings of the Fourth IEEE International Conference on Biometrics: Theory Applications and Systems, 2010

2009
Entropy Decoding Processor for Modern Multimedia Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Trace-driven workload simulation method for Multiprocessor System-On-Chips.
Proceedings of the 46th Design Automation Conference, 2009

2008
Low Cost SoC Design of H.264/AVC Decoder for Handheld Video Player.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A Multiprocessor SoC Architecture with Efficient Communication Infrastructure and Advanced Compiler Support for Easy Application Development.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007
H.264/AVC decoder SoC towards the low cost mobile video player.
Proceedings of the 2007 IEEE International SOC Conference, 2007

2005
A Fingerprint Matching Using Minutia Ridge Shape for Low Cost Match-on-Card Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

New Macroblock Engine Architecture for Video Processing.
Proceedings of the IAPR Conference on Machine Vision Applications (IAPR MVA 2005), 2005

A Hybrid Method for Fingerprint Image Quality Calculation.
Proceedings of the Fourth IEEE Workshop on Automatic Identification Advanced Technologies (AutoID 2005), 2005

2002
New Rate Control Method with Minimum Skipped Frames for Very Low Delay in H.263+ Codec.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Realization of fingerprint identification module on DSP board.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

High density bit-serial FPGA with LUT embedding shift register function.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

A new methodology for low delay real-time videophone software architecture design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Efficient method for face region quality enhancement in low bit rate video coding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
H.263+ Video Encoder/Decoder LSI Featuring System-MSPA Architecture and Improved Rate Control Method.
Proceedings of the World Multiconference on Systemics, Cybernetics and Informatics, 2001

1999
Motion Estimator LSI for MPEG2 High Level Standard.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
Towards one chip HDTV MPEG2 encoder LSI.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1995
Automatic design for bit-serial MSPA architecture.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995


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