Dongjoo Shin
Orcid: 0000-0002-4594-0560
According to our database1,
Dongjoo Shin
authored at least 35 papers
between 2014 and 2022.
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Bibliography
2022
Development of Force Sensor System Based on Tri-Axial Fiber Bragg Grating with Flexure Structure.
Sensors, 2022
Flexible and Stretchable Optical Fiber Strain Sensor based on Nanoparticles and Polymer for Human Motion Detection.
Proceedings of the IEEE International Symposium on Medical Measurements and Applications, 2022
Proceedings of the IEEE International Symposium on Medical Measurements and Applications, 2022
2021
Wearable Sensor based on Fiber Bragg Grating with Flexible Polymer for Squat Exercise.
Proceedings of the IEEE International Workshop on Metrology for Industry 4.0 & IoT, 2021
2020
The Hardware and Algorithm Co-Design for Energy-Efficient DNN Processor on Edge/Mobile Devices.
IEEE Trans. Circuits Syst., 2020
Proc. IEEE, 2020
Proceedings of the 2020 IEEE International Workshop on Metrology for Industry 4.0 & IoT, 2020
2019
UNPU: An Energy-Efficient Deep Neural Network Accelerator With Fully Variable Weight Bit Precision.
IEEE J. Solid State Circuits, 2019
A Full HD 60 fps CNN Super Resolution Processor with Selective Caching based Layer Fusion for Mobile Devices.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Development and Evaluation of Tri-Axial Fiber Bragg Grating in a Measurement Module for Catheterization.
Proceedings of the 2nd Workshop on Metrology for Industry 4.0 and IoT MetroInd4.0&IoT 2019, 2019
A 2.1TFLOPS/W Mobile Deep RL Accelerator with Transposable PE Array and Experience Compression.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
A 0.55 V 1.1 mW Artificial Intelligence Processor With On-Chip PVT Compensation for Autonomous Mobile Robots.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
DNPU: An Energy-Efficient Deep-Learning Processor with Heterogeneous Multi-Core Architecture.
IEEE Micro, 2018
Proceedings of the 2018 IEEE International Symposium on Medical Measurements and Applications, 2018
UNPU: A 50.6TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 46.1 fps Global Matching Optical Flow Estimation Processor for Action Recognition in Mobile Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 1.41mW on-chip/off-chip hybrid transposition table for low-power robust deep tree search in artificial intelligence SoCs.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
14.2 DNPU: An 8.1TOPS/W reconfigurable CNN-RNN processor for general-purpose deep neural networks.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
An energy-efficient deep learning processor with heterogeneous multi-core architecture for convolutional neural networks and recurrent neural networks.
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017
A 21mW low-power recurrent neural network accelerator with quantization tables for embedded deep learning applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
A 2.71 nJ/Pixel Gaze-Activated Object Recognition System for Low-Power Mobile Smart Glasses.
IEEE J. Solid State Circuits, 2016
14.3 A 0.55V 1.1mW artificial-intelligence processor with PVT compensation for micro robots.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
A 1.1 mW 32-thread artificial intelligence processor with 3-level transposition table and on-chip PVT compensation for autonomous mobile robots.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016
2015
An Energy-Efficient and Scalable Deep Learning/Inference Processor With Tetra-Parallel MIMD Architecture for Big Data Applications.
IEEE Trans. Biomed. Circuits Syst., 2015
Proceedings of the Symposium on VLSI Circuits, 2015
4.6 A1.93TOPS/W scalable deep learning/inference processor with tetra-parallel MIMD architecture for big-data applications.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
18.1 A 2.71nJ/pixel 3D-stacked gaze-activated object-recognition system for low-power mobile HMD applications.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A keypoint-level parallel pipelined object recognition processor with gaze activation image sensor for mobile smart glasses system.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015
2014
A Wearable Neuro-Feedback System With EEG-Based Mental Status Monitoring and Transcranial Electrical Stimulation.
IEEE Trans. Biomed. Circuits Syst., 2014
18.5 A 2.14mW EEG neuro-feedback processor with transcranial electrical stimulation for mental-health management.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
10.4 A 1.22TOPS and 1.52mW/MHz augmented reality multi-core processor with neural network NoC for HMD applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
An 1.92mW Feature Reuse Engine based on inter-frame similarity for low-power object recognition in video frames.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014