Donghyun Kim

Affiliations:
  • Qualcomm, Inc., San Diego, CA, USA
  • Korea Advanced Institute of Science and Technology, KAIST, School of Electrical and Computer Science, Daejeon, Korea (PhD 2006)


According to our database1, Donghyun Kim authored at least 33 papers between 2003 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.
IEEE J. Solid State Circuits, 2015

2014

2011
A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
Visual Image Processing RAM: Memory Architecture With 2-D Data Location Search and Data Consistency Management for a Multicore Object Recognition Processor.
IEEE Trans. Circuits Syst. Video Technol., 2010

A 116 fps/74 mW Heterogeneous 3D-Media Processor for 3-D Display Applications.
IEEE J. Solid State Circuits, 2010

2009
A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2009

81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC.
IEEE Trans. Very Large Scale Integr. Syst., 2009

A Floating-Point Unit for 4D Vector Inner Product with Reduced Latency.
IEEE Trans. Computers, 2009

Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor.
IET Comput. Digit. Tech., 2009

Shader-based tessellation to save memory bandwidth in a mobile multimedia processor.
Comput. Graph., 2009

A 201.4GOPS 496mW real-time multi-object recognition processor with bio-inspired neural perception engine.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
An Area Efficient Early Z -Test Method for 3-D Graphics Rendering Hardware.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A 36 fps SXGA 3-D Display Processor Embedding a Programmable 3-D Graphics Rendering Engine.
IEEE J. Solid State Circuits, 2008

Area-efficient pixel rasterization and texture coordinate interpolation.
Comput. Graph., 2008

A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual-Attention Engine.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor.
Proceedings of the 45th Design Automation Conference, 2008

A 3D graphics processor with fast 4D vector inner product units and power aware texture cache.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Tessellation-enabled shader for a bandwidth-limited 3D graphics engine.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
An Energy-Efficient Mobile Vertex Processor With Multithread Expanded VLIW Architecture and Vertex Caches.
IEEE J. Solid State Circuits, 2007

Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics Hardware.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Visual image processing RAM for fast 2-D data location search.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

A 186Mvertices/s 161mW Floating-Point Vertex Processor for Mobile Graphics Systems.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications.
IEEE J. Solid State Circuits, 2006

A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A 33.2M vertices/sec programmable geometry engine for multimedia embedded systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 3-way SIMD engine for programmable triangle setup in embedded 3D graphics hardware.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An 11M-triangles/sec 3D graphics clipping engine for triangle primitives.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
An Efficient Fragment Processing Technique in A-Buffer Implementation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2004

Division-free rasterizer for perspective-correct texture filtering.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A hardware-like high-level language based environment for 3D graphics architecture exploration.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003


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