Donghyun Kim
Affiliations:- Qualcomm, Inc., San Diego, CA, USA
- Korea Advanced Institute of Science and Technology, KAIST, School of Electrical and Computer Science, Daejeon, Korea (PhD 2006)
According to our database1,
Donghyun Kim
authored at least 33 papers
between 2003 and 2015.
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2015
Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming.
IEEE J. Solid State Circuits, 2015
2014
19.5 Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2011
A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache.
IEEE Trans. Very Large Scale Integr. Syst., 2011
2010
Visual Image Processing RAM: Memory Architecture With 2-D Data Location Search and Data Consistency Management for a Multicore Object Recognition Processor.
IEEE Trans. Circuits Syst. Video Technol., 2010
IEEE J. Solid State Circuits, 2010
2009
A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Computers, 2009
Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor.
IET Comput. Digit. Tech., 2009
Comput. Graph., 2009
A 201.4GOPS 496mW real-time multi-object recognition processor with bio-inspired neural perception engine.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
A 36 fps SXGA 3-D Display Processor Embedding a Programmable 3-D Graphics Rendering Engine.
IEEE J. Solid State Circuits, 2008
Comput. Graph., 2008
A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual-Attention Engine.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor.
Proceedings of the 45th Design Automation Conference, 2008
A 3D graphics processor with fast 4D vector inner product units and power aware texture cache.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
An Energy-Efficient Mobile Vertex Processor With Multithread Expanded VLIW Architecture and Vertex Caches.
IEEE J. Solid State Circuits, 2007
Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC.
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A 3-way SIMD engine for programmable triangle setup in embedded 3D graphics hardware.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2004
Division-free rasterizer for perspective-correct texture filtering.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
A hardware-like high-level language based environment for 3D graphics architecture exploration.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003