Donghoon Yoo

Orcid: 0000-0001-6997-2658

According to our database1, Donghoon Yoo authored at least 19 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
General Bootstrapping Approach for RLWE-Based Homomorphic Encryption.
IEEE Trans. Computers, January, 2024

Adaptive Successive Over-Relaxation Method for a Faster Iterative Approximation of Homomorphic Operations.
IACR Cryptol. ePrint Arch., 2024

2023
Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023

Medha: Microcoded Hardware Accelerator for computing on Encrypted Data.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

2022
Efficient FHEW Bootstrapping with Small Evaluation Keys, and Applications to Threshold Homomorphic Encryption.
IACR Cryptol. ePrint Arch., 2022

Privacy-Preserving Machine Learning With Fully Homomorphic Encryption for Deep Neural Network.
IEEE Access, 2022

2021
Accelerator for Computing on Encrypted Data.
IACR Cryptol. ePrint Arch., 2021

2018
Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems.
ACM Trans. Archit. Code Optim., 2018

2016
TQSIM: A fast cycle-approximate processor simulator based on QEMU.
J. Syst. Archit., 2016

2014
Shading language compiler implementation for mobile ray tracing accelerator.
Proceedings of the SIGGRAPH Asia 2014 Mobile Graphics and Interactive Applications, 2014

Nop compression scheme for high speed DSPs based on VLIW architecture.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

Retargetable automatic generation of compound instructions for CGRA based reconfigurable processor applications.
Proceedings of the 2014 International Conference on Compilers, 2014

2013
A scalable scheduling algorithm for coarse-grained reconfigurable architecture.
Proceedings of the IEEE International Conference on Consumer Electronics, 2013

Efficient high throughput rate cross-correlation logic design for sign-bit reference waveforms.
Proceedings of the IEEE International Conference on Consumer Electronics, 2013

The acceleration of various multimedia applications on reconfigurable processor.
Proceedings of the IEEE International Conference on Consumer Electronics, 2013

An OpenCL optimizing compiler for reconfigurable processors.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2012
SCC based modulo scheduling for coarse-grained reconfigurable processors.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Function inlining and loop unrolling for loop acceleration in reconfigurable processors.
Proceedings of the 15th International Conference on Compilers, 2012

2011
An instruction-scheduling-aware data partitioning technique for coarse-grained reconfigurable architectures.
Proceedings of the ACM SIGPLAN/SIGBED 2011 conference on Languages, 2011


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