Dong-U Lee

According to our database1, Dong-U Lee authored at least 33 papers between 2002 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2015
Automated Iterative Pipelining for ASIC Design.
ACM Trans. Design Autom. Electr. Syst., 2015

2012
Precision-Aware Self-Quantizing Hardware Architectures for the Discrete Wavelet Transform.
IEEE Trans. Image Process., 2012

2009
Hierarchical Segmentation for Hardware Function Evaluation.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Energy-Efficient Image Compression for Resource-Constrained Platforms.
IEEE Trans. Image Process., 2009

Optimized Custom Precision Function Evaluation for Embedded Processors.
IEEE Trans. Computers, 2009

2008
Pilotless Frame Synchronization for LDPC-Coded Transmission Systems.
IEEE Trans. Signal Process., 2008

Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations.
IEEE Trans. Computers, 2008

Energy-Aware High Resolution Image Acquisition via Heterogeneous Image Sensors.
IEEE J. Sel. Top. Signal Process., 2008

Design Tradeoffs and Hardware Architecture for Real-Time Iterative MIMO Detection using Sphere Decoding and LDPC Coding.
IEEE J. Sel. Areas Commun., 2008

2007
A Flexible Architecture for Precise Gamma Correction.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method.
IEEE Trans. Very Large Scale Integr. Syst., 2007

A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation.
IEEE Trans. Computers, 2007

Pilotless Frame Synchronization via LDPC Code Constraint Feedback.
IEEE Commun. Lett., 2007

Energy-optimized image communication on resource-constrained sensor platforms.
Proceedings of the 6th International Conference on Information Processing in Sensor Networks, 2007

2006
Accuracy-Guaranteed Bit-Width Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis.
IEEE Trans. Computers, 2006

Joint LDPC decoding and timing recovery using code constraint feedback.
IEEE Commun. Lett., 2006

Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2005
A hardware Gaussian noise generator using the Wallace method.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Optimizing Hardware Function Evaluation.
IEEE Trans. Computers, 2005

Reconfigurable Acceleration for Monte Carlo Based Financial Simulation.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Ziggurat-based Hardware Gaussian Random Number Generator.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

MiniBit: bit-width optimization via affine arithmetic.
Proceedings of the 42nd Design Automation Conference, 2005

Automating custom-precision function evaluation for embedded processors.
Proceedings of the 2005 International Conference on Compilers, 2005

2004
Hardware designs for function evaluation and LDPC coding.
PhD thesis, 2004

A Gaussian Noise Generator for Hardware-Based Simulations.
IEEE Trans. Computers, 2004

Adaptive range reduction for hardware function evaluation.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs.
Proceedings of the Field Programmable Logic and Application, 2004

A Flexible Hardware Encoder for Low-Density Parity-Check Codes.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003
Hierarchical segmentation schemes for function evaluation.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Non-uniform Segmentation for Hardware Function Evaluation.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A Hardware Gaussian Noise Generator for Channel Code Evaluation.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

2002
Incremental programming for reconfigurable engines.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002


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