Dong-Shong Liang

According to our database, Dong-Shong Liang authored at least 12 papers between 2005 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

Numerical Analysis of the Effect of Thin-Film Thickness and Material in Field Mapping of Eddy-Current Probes Using Photoinductive Technique.

Yen-Lin Pan, Cheng-Chi Tai, Dong-Shong Liang

IEICE Trans. Electron., 2012

2010

Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources.

Kwang-Jow Gan, Dong-Shong Liang, Yan-Wun Chen

IEICE Trans. Inf. Syst., 2010

Investigation of Adjustable Current-Voltage Characteristics and Hysteresis Phenomena for Multiple-Peak Negative Differential Resistance Circuit.

Kwang-Jow Gan, Dong-Shong Liang

IEICE Trans. Electron., 2010

2009

Standard BiCMOS Implementation of a Two-Peak Negative Differential Resistance Circuit with High and Adjustable Peak-to-Valley Current Ratio.

Dong-Shong Liang, Kwang-Jow Gan, Cheng-Chi Tai, Cher-Shiung Tsai

IEICE Trans. Electron., 2009

Multiple-Valued Memory Design by Standard BiCMOS Technique.

Dong-Shong Liang, Kwang-Jow Gan, Jenq-Jong Lu, Cheng-Chi Tai, Cher-Shiung Tsai, Geng-Huang Lan, Yaw-Hwang Chen

Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

2008

New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits.

Dong-Shong Liang, Kwang-Jow Gan

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2006

The Design of MOS-NDR-Based Cellular Neural Network.

Dong-Shong Liang, Yaw-Hwang Chen, Chun-Min Wen, Chun-Da Tu, Kwang-Jow Gan, Cher-Shiung Tsai

Proceedings of the International Joint Conference on Neural Networks, 2006

Design of AND and NAND Logic Gate Using NDR-BASED Circuit Suitable for CMOS Process.

Dong-Shong Liang, Cheng-Chi Tai, Kwang-Jow Gan, Cher-Shiung Tsai, Yaw-Hwang Chen

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Five-State Logic Using MOS-HBT-NDR Circuit by Standard SiGe BiCMOS Process.

Kwang-Jow Gan, Dong-Shong Liang, Cher-Shiung Tsai, Yaw-Hwang Chen, Chun-Ming Wen

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Four-Valued Memory Circuit Designed by Multiple-Peak MOS-NDR Devices and Circuits.

Dong-Shong Liang, Kwang-Jow Gan, Long-Xian Su, Chi-Pin Chen, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Novel Voltage-Controlled Oscillator Design by MOS-NDR Devices and Circuits.

Dong-Shong Liang, Kwang-Jow Gan, Chung-Chih Hsiao, Cher-Shiung Tsai, Yaw-Hwang Chen, Shih-Yu Wang, Shun-Huo Kuo, Feng-Chang Chiang, Long-Xian Su

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process.

Kwang-Jow Gan, Dong-Shong Liang, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, Chi-Pin Chen

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005