Dong-Ryeol Oh
Orcid: 0000-0002-5454-5191
According to our database1,
Dong-Ryeol Oh
authored at least 10 papers
between 2008 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2024
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC.
IEEE J. Solid State Circuits, August, 2024
2022
IEEE J. Solid State Circuits, 2022
A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS.
IEEE J. Solid State Circuits, 2021
2020
IEEE Trans. Circuits Syst., 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration.
IEEE J. Solid State Circuits, 2019
2015
IEEE J. Solid State Circuits, 2015
Proceedings of the ESSCIRC Conference 2015, 2015
2008