Dong Hyun Baik

According to our database, Dong Hyun Baik authored at least 9 papers between 2003 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan.

Kim T. Le, Dong Hyun Baik, Kewal K. Saluja

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

Test Cost Reduction Using Partitioned Grid Random Access Scan.

Dong Hyun Baik, Kewal K. Saluja

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005

Yield-Driven, False-Path-Aware Clock Skew Scheduling.

Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja

IEEE Des. Test Comput., 2005

False Path and Clock Scheduling Based Yield-Aware Gate Sizing.

Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Progressive random access scan: a simultaneous solution to test power, test data volume and test time.

Dong Hyun Baik, Kewal K. Saluja

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size.

Dong Hyun Baik, Kewal K. Saluja

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Random Access Scan: A solution to test power, test data volume and test time.

Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A yield improvement methodology using pre- and post-silicon statistical clock scheduling.

Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003

Exclusive Test and its Applications to Fault Diagnosis.

Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003