Dong-Hyeon Park

Orcid: 0000-0003-3052-6890

According to our database1, Dong-Hyeon Park authored at least 8 papers between 2017 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Optimizing Sparse Linear Algebra on Reconfigurable Architecture.
PhD thesis, 2021

CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits, 2020

Sparse-TPU: adapting systolic arrays for sparse matrices.
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018
OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Accelerating Smith-Waterman Alignment Workload with Scalable Vector Computing.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017


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