Dondee Navarro
Orcid: 0000-0001-6167-9617
According to our database1,
Dondee Navarro
authored at least 16 papers
between 2005 and 2021.
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Bibliography
2021
Simulation-Based Power-Loss Optimization of General-Purpose High-Voltage SiC MOSFET Circuit Under High-Frequency Operation.
IEEE Access, 2021
2020
Prediction of DC-AC Converter Efficiency Degradation due to Device Aging Using a Compact MOSFET-Aging Model.
IEICE Trans. Electron., 2020
2019
Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs.
IEICE Trans. Electron., 2019
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
2018
Compact modeling of dynamic trap density evolution for predicting circuit-performance aging.
Microelectron. Reliab., 2018
Self-controlled walking robot with gyro sensor network for stable movement on non-smooth surfaces.
Proceedings of the 2018 IEEE International Conference on Simulation, 2018
Proceedings of the 48th European Solid-State Device Research Conference, 2018
2017
Modeling of dynamic trap density increase for aging simulation of any MOSFET circuits.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2009
IPSJ Trans. Syst. LSI Des. Methodol., 2009
2008
Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations.
Math. Comput. Simul., 2008
2007
Shot Noise Modeling in Metal-Oxide-Semiconductor Field Effect Transistors under Sub-Threshold Condition.
IEICE Trans. Electron., 2007
2005
A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential.
IEICE Trans. Electron., 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005