Donald Yeung
Orcid: 0000-0003-0341-2644Affiliations:
- University of Maryland, College Park, USA
According to our database1,
Donald Yeung
authored at least 54 papers
between 1992 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on orcid.org
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on ece.umd.edu
On csauthors.net:
Bibliography
2024
MORSE: Memory Overwrite Time Guided Soft Writes to Improve ReRAM Energy and Endurance.
Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, 2024
2023
Proceedings of the International Symposium on Memory Systems, 2023
2021
ACM Trans. Archit. Code Optim., 2021
2020
ACM Trans. Archit. Code Optim., 2020
Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020
2019
IEEE Micro, 2019
Proceedings of the International Symposium on Memory Systems, 2019
2018
Proceedings of the International Symposium on Memory Systems, 2018
2017
ACM Trans. Comput. Syst., 2017
IEEE Comput. Archit. Lett., 2017
Proceedings of the 36th IEEE International Performance Computing and Communications Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
ACM Trans. Comput. Syst., 2016
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
2015
Studying the impact of multicore processor scaling on directory techniques via reuse distance analysis.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
2013
Efficient Reuse Distance Analysis of Multicore Scaling for Loop-Based Parallel Programs.
ACM Trans. Comput. Syst., 2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
Identifying optimal multicore cache hierarchies for loop-based parallel programs via reuse distance analysis.
Proceedings of the 2012 ACM SIGPLAN workshop on Memory Systems Performance and Correctness: held in conjunction with PLDI '12, 2012
2011
Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor.
IEEE Comput. Archit. Lett., 2011
Proceedings of the 3rd USENIX Workshop on Hot Topics in Parallelism, 2011
Coherent Profiles: Enabling Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel Programs.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2009
J. Instr. Level Parallelism, 2009
Proceedings of the PACT 2009, 2009
2008
J. Instr. Level Parallelism, 2008
2007
Low Power System Design by Combining Software Prefetching and Dynamic voltage Scaling.
J. Circuits Syst. Comput., 2007
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007
2006
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006
2005
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005
2004
A study of source-level compiler algorithms for automatic construction of pre-execution code.
ACM Trans. Comput. Syst., 2004
A general framework for prefetch scheduling in linked data structures and its application to multi-chain prefetching.
ACM Trans. Comput. Syst., 2004
The Efficacy of Software Prefetching and Locality Optimizations on Future Memory Systems.
J. Instr. Level Parallelism, 2004
Transferring performance gain from software prefetching to energy reduction.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors.
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004
2003
J. Instr. Level Parallelism, 2003
2002
Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), 2002
Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002
2001
IEEE Trans. Parallel Distributed Syst., 2001
Evaluating the impact of memory system performance on software prefetching and locality optimizations.
Proceedings of the 15th international conference on Supercomputing, 2001
Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes.
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001
2000
1999
Proceedings of the 13th international conference on Supercomputing, 1999
1998
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998
1996
Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996
1995
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995
1994
Proceedings of the Multithreaded Computer Architecture, 1994
1993
IEEE Micro, 1993
Experience with Fine-Grain Synchronization in MIMD Machines for Preconditioned Conjugate Gradient.
Proceedings of the Fourth ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming (PPOPP), 1993
1992
Proceedings of the Parallel Symbolic Computing: Languages, 1992