Donald W. Plass

According to our database¹, Donald W. Plass authored at least 24 papers between 1993 and 2018.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2018

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2018

2017

3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4.

[BibT_eX]

[DOI]

Christopher J. Gonzalez

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2016

2015

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2015

IBM POWER8 circuit design and energy optimization.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2015

IBM z13 circuit design and methodology.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2015

4.1 22nm Next-generation IBM System z microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

5.5GHz system z microprocessor and multi-chip module.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

Isolated Preset Architecture for a 32nm SOI embedded DRAM macro.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2012

2011

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2011

A 5.2GHz microprocessor chip for the IBM zEnterprise™ system.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

2008

An on-chip dual supply charge pump system for 45nm PD SOI eDRAM.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2008, 2008

2007

IBM POWER6 SRAM arrays.

[BibT_eX]

[DOI]

Donald W. Plass

Yuen H. Chan

IBM J. Res. Dev., 2007

Design of the Power6 Microprocessor.

[BibT_eX]

[DOI]

Mary Yvonne Lanzerotti

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2004

Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell.

[BibT_eX]

[DOI]

Proceedings of the 33rd European Solid-State Circuits Conference, 2004

Design and implementation of the POWER5 microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2000

Design validation of .18 μm 1 GHz cache and register arrays.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1993

Design SRAMs for burn-in.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Donald W. Plass

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