Donald Paterson

According to our database, Donald Paterson authored at least 17 papers between 2002 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A -90-dBFS-IM₃, -164-dBFS/Hz-NSD, 700-MHz-Bandwidth Continuous-Time Pipelined ADC With Digital Cancellation of DAC Errors.

Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Prawal Shrestha, Zhao Li, Sevil Zeynep Lulec, Konstantinos Vasilakopoulos, Raviteja Theertham, Donald Paterson, Qingnan Yu, Aseer Chowdhury

IEEE J. Solid State Circuits, December, 2024

22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors.

Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Qingnan Yu, Zhao Li, Zeynep Lulec, Konstantinos Vasilakopoulos, Prawal Shrestha, Donald Paterson, Raviteja Theertham, Aseer Chowdhury

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022

Critical damages identification in a multi-level damage stability assessment framework for passenger ships.

Francesco Mauro, Dracos Vassalos, Donald Paterson

Reliab. Eng. Syst. Saf., 2022

2020

16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter.

Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya S. Bhat, Shanthi Pavan

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2017

A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD.

Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Haiyang Zhu, Donald Paterson, Jialin Zhao, Sharvil Patil, Shanthi Pavan

IEEE J. Solid State Circuits, 2017

A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology.

Siddharth Devarajan, Larry Singer, Dan Kelly, Tao Pan, José B. Silva, Janet Brunsilius, Daniel Rey-Losada, Frank Murden, Carroll Speir, Jeff Bray, Eric Otte, Nevena Rakuljic, Phil Brown, Todd Weigandt, Qicheng Yu, Donald Paterson, Corey Petersen, Jeffrey C. Gealow, Gabriele Manganaro

IEEE J. Solid State Circuits, 2017

16.2 A 9GS/s 1GHz-BW oversampled continuous-time pipeline ADC achieving -161dBFS/Hz NSD.

Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Haiyang Zhu, Donald Paterson

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology.

Siddharth Devarajan, Larry Singer, Dan Kelly, Steve Kosic, Tao Pan, José B. Silva, Janet Brunsilius, Daniel Rey-Losada, Frank Murden, Carroll Speir, Jeff Bray, Eric Otte, Nevena Rakuljic, Phil Brown, Todd Weigandt, Qicheng Yu, Donald Paterson, Corey Petersen, Jeffrey C. Gealow

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS.

Yunzhi Dong, José B. Silva, Qingdong Meng, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Zhao Li, Donald Paterson, Jeffrey C. Gealow

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS.

Yunzhi Dong, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Zhao Li, Richard Schreier, Qingdong Meng, José B. Silva, Donald Paterson, Jeffrey C. Gealow

IEEE J. Solid State Circuits, 2016

15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS.

Yunzhi Dong, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Richard Schreier, Qingdong Meng, José B. Silva, Donald Paterson, Jeffrey C. Gealow

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2012

A DC-to-1 GHz Tunable RF Delta Sigma ADC Achieving DR = 74 dB and BW = 150 MHz at f₀ = 450 MHz Using 550 mW.

Hajime Shibata, Richard Schreier, Wenhua Yang, Ali Shaikh, Donald Paterson, Trevor C. Caldwell, David Alldred, Ping Wing Lai

IEEE J. Solid State Circuits, 2012

A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mW.

Hajime Shibata, Richard Schreier, Wenhua Yang, Ali Shaikh, Donald Paterson, Trevor C. Caldwell, David Alldred, Ping Wing Lai

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2006

A 375-mW Quadrature Bandpass$\Delta\Sigma$ADC With 8.5-MHz BW and 90-dB DR at 44 MHz.

Richard Schreier, Nazmy Abaskharoun, Hajime Shibata, Donald Paterson, Steven Rose, Iuri Mehr, Qui Luu

IEEE J. Solid State Circuits, 2006

A 375mW Quadrature Bandpass ΔΣ ADC with 90dB DR and 8.5MHz BW at 44MHz.

Richard Schreier, Nazmy Abaskharoun, Hajime Shibata, Iuri Mehr, Steve Rose, Donald Paterson

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2002

A 10-300-MHz IF-digitizing IC with 90-105-dB dynamic range and 15-333-kHz bandwidth.

Richard Schreier, Jennifer Lloyd, Larry Singer, Donald Paterson, Mike Timko, Michael Hensley, Greg Patterson, Kevin Behel, James Zhou

IEEE J. Solid State Circuits, 2002

A 12-bit integrated analog front end for broadband wireline networks.

Iuri Mehr, Prabir C. Maulik, Donald Paterson

IEEE J. Solid State Circuits, 2002