Donald E. Thomas

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2015

Keynote speaker moving digital system design courses into the modern era, again.

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[DOI]

Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

Statistical Learning in Chip (SLIC).

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Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014

Cost-effective lifetime and yield optimization for NoC-based MPSoCs.

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[DOI]

ACM Trans. Design Autom. Electr. Syst., 2014

SLIC: Statistical learning in chip.

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[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Ultra-low-power biomedical circuit design and optimization: Catching the don't cares.

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[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Low-power hardware implementation of movement decoding for brain computer interface with reduced-resolution discrete cosine transform.

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Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

2012

Lifetime improvement through runtime wear-based task mapping.

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[DOI]

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2010

Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors.

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[DOI]

IEEE Trans. Computers, 2010

Slack allocation for yield improvement in NoC-based MPSoCs.

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[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs.

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[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

A case for lifetime-aware task mapping in embedded chip multiprocessors.

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[DOI]

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009

Rethinking the synthesis of buses, data mapping, and memory allocation for MPSoC.

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[DOI]

Des. Autom. Embed. Syst., 2009

2007

Rethinking Automated Synthesis of MPSoC Architectures.

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[DOI]

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Shared Resource Access Attributes for High-Level Contention Models.

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[DOI]

Proceedings of the 44th Design Automation Conference, 2007

Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC.

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[DOI]

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Event-based re-training of statistical contention models for heterogeneous multiprocessors.

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[DOI]

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006

Scenario-oriented design for single-chip heterogeneous multiprocessors.

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[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

2005

High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors.

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[DOI]

Andrew S. Cassidy

ACM Trans. Design Autom. Electr. Syst., 2005

Undergraduate embedded system education at Carnegie Mellon.

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[DOI]

ACM Trans. Embed. Comput. Syst., 2005

2004

Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach.

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Proceedings of the 2004 Design, 2004

High level cache simulation for heterogeneous multiprocessors.

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[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Benchmark-based design strategies for single chip heterogeneous multiprocessors.

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[DOI]

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

Layered, Multi-Threaded, High-Level Performance Design.

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[DOI]

Andrew S. Cassidy

Proceedings of the 2003 Design, 2003

Schedulers as model-based design elements in programmable heterogeneous multiprocessors.

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[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

System-Level Modeling of a Network Switch SoC.

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[DOI]

Andrew S. Cassidy

Christopher P. Andrews

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Multi-Level Modeling of Software on Hardware in Concurrent Computation.

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[DOI]

Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems.

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Proceedings of the 2002 Design, 2002

The design context of concurrent computation systems.

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[DOI]

Christopher M. Eatedali

Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001

Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device.

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[DOI]

Sandra J. Weber

IEEE Trans. Very Large Scale Integr. Syst., 2001

Modeling and simulation of steady state and transient behaviors for emergent SoCs.

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[DOI]

Arne J. Suppé

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Modeling and evaluation of hardware/software designs.

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[DOI]

Neal K. Tibrewala

Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000

Memory modeling for system synthesis.

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[DOI]

Sari L. Coumeri

IEEE Trans. Very Large Scale Integr. Syst., 2000

A codesign virtual machine for hierarchical, balanced hardware/software system modeling.

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[DOI]

Simon N. Peffers

Proceedings of the 37th Conference on Design Automation, 2000

Unifying behavioral synthesis and physical design.

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[DOI]

William E. Dougherty

Proceedings of the 37th Conference on Design Automation, 2000

Frequency interleaving as a codesign scheduling paradigm.

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[DOI]

Simon N. Peffers

Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999

Subsetting Behavioral Intellectual Property for Low Power ASIP Design.

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[DOI]

William E. Dougherty

David J. Pursley

J. VLSI Signal Process., 1999

Modeling and automating selection of guarding techniques for datapath elements.

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[DOI]

William E. Dougherty

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

An Environment for Exploring Low Power Memory Configurations in System Level Design.

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[DOI]

Sari L. Coumeri

Proceedings of the IEEE International Conference On Computer Design, 1999

Vertical Benchmarks for CAD.

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[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Peer-based multithreaded executable co-specification.

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[DOI]

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998

Address generation for memories containing multiple arrays.

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[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Managing Pipeline-Reconfigurable FPGAs.

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[DOI]

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1997

Synthesis of application-specific memory designs.

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[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1997

1996

The Design of Mixed Hardware/Software Systems.

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[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

The Verilog hardware description language (3. ed.).

[BibT_eX]

Philip Moorby

Kluwer, ISBN: 978-0-7923-9723-6, 1996

1995

Array mapping in behavioral synthesis.

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[DOI]

Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Multiple-process behavioral synthesis for mixed hardware-software systems.

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[DOI]

Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Execution-time profiling for multiple-process behavioral synthesis.

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[DOI]

John Alan Miller

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Hidden Markov modeling and fuzzy controllers in FPGAs.

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[DOI]

Proceedings of the 3rd IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '95), 1995

Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs.

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[DOI]

Prashant Sawkar

Proceedings of the 32st Conference on Design Automation, 1995

The Verilog hardware description language (2. ed.).

[BibT_eX]

Philip Moorby

Kluwer, ISBN: 978-0-7923-9523-2, 1995

1994

Exploiting the special structure of conflict and compatibility graphs in high-level synthesis.

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[DOI]

D. L. Springer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Behavioral-Test Generation using Mixed-Integer Non-linear Programming.

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[DOI]

R. S. Ramchandani

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Applications of attributed-behavior synthesis.

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[DOI]

Lawrence F. Arnstein

Proceedings of the 7th International Symposium on High Level Synthesis, 1994

The Attributed-Behavior Abstraction and Synthesis Tools.

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[DOI]

Lawrence F. Arnstein

Proceedings of the 31st Conference on Design Automation, 1994

1993

A dynamic approach to controlling high-level synthesis CAD tools.

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[DOI]

Anthony J. Gadient

IEEE Trans. Very Large Scale Integr. Syst., 1993

A Model and Methodology for Hardware-Software Codesign.

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[DOI]

IEEE Des. Test Comput., 1993

A general consistency technique for increasing the controllability of high level synthesis tools.

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[DOI]

Lawrence F. Arnstein

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Performance Directed Technology Mapping for Look-Up Table Based FPGAs.

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[DOI]

Prashant Sawkar

Proceedings of the 30th Design Automation Conference. Dallas, 1993

Synthesis of Pipelined Instruction Set Processors.

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[DOI]

Richard J. Cloutier

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Addressing the Tradeoff Between Standard and Custom ICs in System Level Design.

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[DOI]

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays.

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[DOI]

Prashant Sawkar

Proceedings of the 29th Design Automation Conference, 1992

1991

Architectural partitioning for system level synthesis of integrated circuits.

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[DOI]

Elizabeth D. Lagnese

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

New methods for coloring and clique partitioning in data path allocation.

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[DOI]

David Springer

Integr., 1991

1990

The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm.

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[DOI]

Richard J. Cloutier

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

Behavioral transformation for algorithmic level IC design.

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[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Architectural Partitioning for System Level Design.

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[DOI]

Elizabeth D. Lagnese

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

The System Architect's Workbench.

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[DOI]

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

CORAL II: Linking Behavior and Structure in an IC Design System.

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[DOI]

Robert L. Blackburn

Patti M. Koenig

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

Linking the Behavioral and Structural Domains of Representation for Digital System Design.

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[DOI]

Robert L. Blackburn

Jayanth V. Rajan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1985

A model of design representation and synthesis.

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[DOI]

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

Synthesis by delayed binding of decisions.

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[DOI]

Jayanth V. Rajan

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

The VLSI design automation assistant: what's in a knowledge base.

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[DOI]

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

Linking the behavioral and structural dominis of representation in a synthesis system.

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[DOI]

Robert L. Blackburn

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

Observations on comparing digital systems synthesis techniques.

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[DOI]

Proceedings of the 13th ACM Annual Conference on Computer Science, 1985

1984

Probing the State of the Art.

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[DOI]

Richard M. Sedmak

IEEE Des. Test, 1984

The VLSI Design Automation Assistant: An IBM System/370 Design.

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[DOI]

IEEE Des. Test, 1984

1983

Defining and Implementing a Multilevel Design Representation with Simulation Applications.

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[DOI]

John A. Nestor

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

Automating Technology Relative Logic Synthesis and Module Selection.

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[DOI]

Gary W. Leive

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

Automatic Data Path Synthesis.

[BibT_eX]

[DOI]

Charles Y. Hitchcock III

Jayanth V. Rajan

Computer, 1983

Behavioral level transformation in the CMU-DA system.

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[DOI]

Proceedings of the 20th Design Automation Conference, 1983

The VLSI Design Automation Assistant: Prototype system.

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[DOI]

Proceedings of the 20th Design Automation Conference, 1983

A method of automatic data path synthesis.

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[DOI]

Charles Y. Hitchcock III

Proceedings of the 20th Design Automation Conference, 1983

1981

Measuring Designer Performance to Verify Design Automation Systems.

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[DOI]

Daniel P. Siewiorek

IEEE Trans. Computers, 1981

A technology relative Logic Synthesis and Module Selection system.

[BibT_eX]

[DOI]

Gary W. Leive

Proceedings of the 18th Design Automation Conference, 1981

1979

The CMU design automation system: An example of automated data path design.

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[DOI]

Proceedings of the 16th Design Automation Conference, 1979

1978

The Use of LSI Modules in Computer Structures: Trends and Limitations.

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[DOI]

Daniel P. Siewiorek

Don L. Scharfetter

Computer, 1978

A technology-relative computer-aided design system: Abstract representations, transformations, and design tradeoffs.

[BibT_eX]

[DOI]

Edward A. Snow

Daniel P. Siewiorek