Don Xie

According to our database1, Don Xie authored at least 28 papers between 2006 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Part-aware Progressive Unsupervised Domain Adaptation for Person Re-Identification.
IEEE Trans. Multim., 2021

2020
PIC-Net: Point Cloud and Image Collaboration Network for Large-Scale Place Recognition.
CoRR, 2020

2018
Three-level pipelined multi-resolution integer motion estimation engine with optimized reference data sharing search for AVS.
J. Real Time Image Process., 2018

2017
Memory interface design for AVS HD video encoder with Level C+ coding order.
IEICE Electron. Express, 2017

Content Adaptive Constraint Based Image Upsampling.
Proceedings of the Advances in Multimedia Information Processing - PCM 2017, 2017

2016
Fast algorithms and VLSI architecture design for HEVC intra-mode decision.
J. Real Time Image Process., 2016

Structure preserving single image super-resolution.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

2015
An adaptive inter CU depth decision algorithm for HEVC.
Proceedings of the 2015 Visual Communications and Image Processing, 2015

2014
Fast algorithm of coding unit depth decision for HEVC intra coding.
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

A Background Modeling Scheme Based on High Efficiency Motion Classification for Surveillance Video Coding.
Proceedings of the Advances in Multimedia Information Processing - PCM 2014, 2014

2013
An Efficient Zigzag Scanning and Entropy Coding Architecture Design.
Proceedings of the Advances in Multimedia Information Processing - PCM 2013, 2013

A highly efficient external memory interface architecture for AVS HD video encoder.
Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, 2013

2012
A flexible and high-performance hardware video encoder architecture.
Proceedings of the 2012 Picture Coding Symposium, 2012

A high speed and efficient architecture of VLD for AVS HD video decoder.
Proceedings of the 2012 Picture Coding Symposium, 2012

An Optimized Hardware Video Encoder for AVS with Level C+ Data Reuse Scheme for Motion Estimation.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

2010
Efficient macroblock pipeline structure in high definition AVS video encoder VLSI architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Variable-Bin-Rate CABAC Engine for H.264/AVC High Definition Real-Time Decoding.
IEEE Trans. Very Large Scale Integr. Syst., 2009

An efficient VLSI architecture for CBAC of AVS HDTV decoder.
Signal Process. Image Commun., 2009

2008
A novel VLSI architecture of motion compensation for multiple standards.
IEEE Trans. Consumer Electron., 2008

2007
A Novel Pipeline Design for H.264 CABAC Decoding.
Proceedings of the Advances in Multimedia Information Processing, 2007

2006
A flexible VLSI architecture of transport processor for an AVS HDTV decoder SoC.
IEEE Trans. Consumer Electron., 2006

An efficient VLSI architecture of VLD for AVS HDTV decoder.
IEEE Trans. Consumer Electron., 2006

Algorithmic and architectural co-design for integer motion estimation of AVS.
IEEE Trans. Consumer Electron., 2006

An AVS HDTV video decoder architecture employing efficient HW/SW partitioning.
IEEE Trans. Consumer Electron., 2006

An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder.
J. Comput. Sci. Technol., 2006

Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard.
J. Comput. Sci. Technol., 2006

A Motion Vector Predictor Architecture for AVS and MPEG-2 HDTV Decoder.
Proceedings of the Advances in Multimedia Information Processing, 2006

An Efficient Reference Frame Storage Scheme for H.264 HDTV Decoder.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006


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