Dominique Borrione
Orcid: 0000-0002-4856-453X
According to our database1,
Dominique Borrione
authored at least 72 papers
between 1976 and 2019.
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Online presence:
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Bibliography
2019
ACM Trans. Embed. Comput. Syst., 2019
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017
2016
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the 2015 Forum on Specification and Design Languages, 2015
2014
A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013
Proceedings of the 2013 Forum on specification and Design Languages, 2013
2010
Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
2009
EURASIP J. Embed. Syst., 2009
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
2008
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008
2007
J. Circuits Syst. Comput., 2007
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study.
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Proceedings of the Forum on specification and Design Languages, 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006
Proceedings of the Forum on specification and Design Languages, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Workshop "Trustworthy Software" 2006, 2006
Proceedings of the Sixth International Workshop on the ACL2 Theorem Prover and its Applications, 2006
2005
Proceedings of the Theorem Proving in Higher Order Logics, 18th International Conference, 2005
Proceedings of the Theorem Proving in Higher Order Logics, 18th International Conference, 2005
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005
Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
2004
TheoSim: combining symbolic simulation and theorem proving for hardware verification.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
Proceedings of the Formal Methods in Computer-Aided Design, 5th International Conference, 2004
Proceedings of the Construction and Analysis of Safe, 2004
2003
Validation of asynchronous circuit specifications using IF/CADP.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003
An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow.
Proceedings of the 36th Hawaii International Conference on System Sciences (HICSS-36 2003), 2003
Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications.
Proceedings of the Forum on specification and Design Languages, 2003
Proceedings of the Correct Hardware Design and Verification Methods, 2003
2002
Improving Static Ordering of BDDs for Reachability Analysis.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the 2002 Design, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
A compositional model for the functional verification of high-level synthesis results.
IEEE Trans. Very Large Scale Integr. Syst., 2000
Using the ACL2 Theorem Prover to Reason about VHDL Components.
RITA, 2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
1999
Design Error Diagnosis in Digital Circuits without Error Model.
Proceedings of the VLSI: Systems on a Chip, 1999
1998
Generation of Tests for the Localization of Single Gate Design Errors in Combinational Circuits using the Stuck-at Fault Model.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998
Formalization of Finite State Machines with Data Path for the Verification of High-Level Synthesis.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998
1997
Proceedings of the European Design and Test Conference, 1997
An approach to Verilog-VHDL interoperability for synchronous designs.
Proceedings of the Advances in Hardware Design and Verification, 1997
1996
A method for automatic design error location and correction in combinational logic circuits.
J. Electron. Test., 1996
Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996
Proceedings of the conference on European design automation, 1996
1995
Proceedings of the Correct Hardware Design and Verification Methods, 1995
Proceedings of the Correct Hardware Design and Verification Methods, 1995
1994
Proceedings of the Proceedings EURO-DAC'94, 1994
1992
IEEE Des. Test Comput., 1992
1989
Zero-Defect Designs, Why and How: Formal Verification vs. Automated Synthesis.
Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989
1988
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988
1983
Lecture Notes in Computer Science 151, Springer, ISBN: 3-540-12275-3, 1983
1982
Proceedings of the 19th Design Automation Conference, 1982
1981
Langages de description de systèmes logiques : propositions pour une méthode formelle de définition.
, 1981
1980
An Overview of CONLAN: A Formal Construction Method for Hardware Description Language.
Proceedings of the Information Processing, Proceedings of the 8th IFIP Congress 1980, Tokyo, Japan - October 6-9, 1980 and Melbourne, Australia, 1980
CONLAN: a formal construction method for hardware description languages: language application.
Proceedings of the American Federation of Information Processing Societies: 1980 National Computer Conference, 1980
CONLAN: a formal construction method for hardware description languages: language derivation.
Proceedings of the American Federation of Information Processing Societies: 1980 National Computer Conference, 1980
CONLAN: a formal construction method for hardware description languages: basic principles.
Proceedings of the American Federation of Information Processing Societies: 1980 National Computer Conference, 1980
1976
LASCAR : un langage pour la simulation et l'évaluation des architectures d'ordinateurs.
PhD thesis, 1976