Dominik Lorenz

Orcid: 0000-0002-6727-1476

According to our database1, Dominik Lorenz authored at least 15 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Scaling Rectified Flow Transformers for High-Resolution Image Synthesis.
CoRR, 2024

Scaling Rectified Flow Transformers for High-Resolution Image Synthesis.
Proceedings of the Forty-first International Conference on Machine Learning, 2024

Adversarial Diffusion Distillation.
Proceedings of the Computer Vision - ECCV 2024, 2024

2023
Stable Video Diffusion: Scaling Latent Video Diffusion Models to Large Datasets.
CoRR, 2023

2022
High-Resolution Image Synthesis with Latent Diffusion Models.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

2019
Unsupervised Part-Based Disentangling of Object Shape and Appearance.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019

2018
Effect of voids on thermo-mechanical reliability of chip resistor solder joints: Experiment, modelling and simulation.
Microelectron. Reliab., 2018

2017
Void Formation and Their Effect on Reliability of Lead-Free Solder Joints on MID and PCB Substrates.
IEEE Trans. Reliab., 2017

2014
Monitoring of aging in integrated circuits by identifying possible critical paths.
Microelectron. Reliab., 2014

2012
Efficiently analyzing the impact of aging effects on large integrated circuits.
Microelectron. Reliab., 2012

2010
Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level (Alterungsanalyse von kombinatorischen Schaltungen auf Gatterebene).
it Inf. Technol., 2010

Aging analysis at gate and macro cell level.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009
Aging analysis of circuit timing considering NBTI and HCI.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008
A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion.
IEEE J. Solid State Circuits, 2008

2007
Variation tolerant high resolution and low latency time-to-digital converter.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007


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