Domine Leenaerts

Affiliations:
  • NXP Semiconductors, Eindhoven, The Netherlands


According to our database1, Domine Leenaerts authored at least 79 papers between 1991 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2024
Full Antenna in Package Solution for 100GHz 6G infrastructure, in 140nm SiGe BiCMOS Technology.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2024

2022
Guest Editorial Introduction to the Special Section on the 2021 RFIC Symposium.
IEEE J. Solid State Circuits, 2022

2021
The future of SiGe BiCMOS: bipolar amplifiers for high-performance millimeter-wave applications.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2021

2020
A 100 Gb/s DC-Coupled Optical Modulator Driver for 3D Photonic Electronic Wafer-Scale Packaging.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2016
A 16-43 GHz low-noise amplifer with 2.5-4.0 dB noise figure.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 30/35 GHz Dual-Band Transmitter for Phased Arrays in Communication/Radar Applications.
IEEE J. Solid State Circuits, 2015

A fully integrated 30GHz 16-QAM single-channel phased array transmitter with 5.9% EVM at 6dB back-off.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
Generalized Semi-Analytical Design Methodology of Class-E Outphasing Power Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 30/35GHz phased array transmitter front-end with >+14dBm Psat and 10° phase/5-bit amplitude resolution for advanced beamforming.
Proceedings of the ESSCIRC 2014, 2014

2013
A Fully Integrated Ka-Band VSAT Down-Converter.
IEEE J. Solid State Circuits, 2013

2012
Broad-Band Odd-Number CMOS Prescalers With Quadrature/Symmetrical Outputs.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 1.95 GHz Sub-1 dB NF, +40 dBm OIP3 WCDMA LNA Module.
IEEE J. Solid State Circuits, 2012

Beamforming techniques and RF transceiver design.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A fully integrated down-converter for Ka-band VSAT satellite reception.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
A 65-nm CMOS Temperature-Compensated Mobility-Based Frequency Reference for Wireless Sensor Networks.
IEEE J. Solid State Circuits, 2011

Advanced transmitters for wireless infrastructure.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 65nm CMOS pulse-width-controlled driver with 8Vpp output voltage for switch-mode RF PAs up to 3.6GHz.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Effects of packaging and process spread on a mobility-based frequency reference in 0.16-μm CMOS.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 1.95GHz sub-1dB NF, +40dBm OIP3 WCDMA LNA with variable attenuation in SiGe: C BiCMOS.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
A 1.2-V 10-μ W NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2°C (3 Sigma ) From - 70°C to 125°C.
IEEE J. Solid State Circuits, 2010

A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010

A 1.2V 10µW NPN-based temperature sensor in 65nm CMOS with an inaccuracy of ±0.2°C (3s) from -70°C to 125°C.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Reconfigurable RF and data converters.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with -82dBm sensitivity for crystal-less wireless sensor nodes.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
Impulse-Based Scheme for Crystal-Less ULP Radios.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios.
IEEE J. Solid State Circuits, 2009

A 65 nm CMOS Inductorless Triple Band Group WiMedia UWB PHY.
IEEE J. Solid State Circuits, 2009

A 65 nm CMOS 30 dBm Class-E RF Power Amplifier With 60% PAE and 40% PAE at 16 dB Back-Off.
IEEE J. Solid State Circuits, 2009

A 65nm CMOS inductorless triple-band-group WiMedia UWB PHY.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 200 µA duty-cycled PLL for wireless sensor nodes.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
The Blixer, a Wideband Balun-LNA-I/Q-Mixer Topology.
IEEE J. Solid State Circuits, 2008

Wideband Balun-LNA With Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling.
IEEE J. Solid State Circuits, 2008

Architectures and Circuit Techniques for Nanoscale RF CMOS (Forum).
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A Wideband Balun LNA I/Q-Mixer combination in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 0.6-to-10GHz Receiver Front-End in 45nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
A Broadband Receive Chain in 65nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A WiMedia-Compliant UWB Transceiver in 65nm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

An inductorless wideband balun-LNA in 65nm CMOS with balanced output.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Accurate Modeling of RF Circuit Blocks: Weakly-Nonlinear Narrowband LNAs.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A fast-hopping single-PLL 3-band MB-OFDM UWB synthesizer.
IEEE J. Solid State Circuits, 2006

Transceiver Design for Multiband OFDM UWB.
EURASIP J. Wirel. Commun. Netw., 2006

2005
An interference-robust receiver for ultra-wideband radio in SiGe BiCMOS technology.
IEEE J. Solid State Circuits, 2005

A 28.5 GHz monolithic cascode LNA with 70GHz f<sub>T</sub> SiGe HBTs.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

A fast-hopping single-PLL 3-band UWB synthesizer in 0.25μm SiGe BiCMOS.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

A low power implementation for the transmit path of a UWB transceiver.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2004

A 10 GHz frequency synthesiser for 802.11a in 0.18 μm CMOS [transceiver applications].
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2003
A 2.4-GHz 0.18-μm CMOS self-biased cascode power amplifier.
IEEE J. Solid State Circuits, 2003

A 15-mW fully integrated I/Q synthesizer for Bluetooth in 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2003

Low power RF IC design for wireless communication.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Mismatch-based timing errors in current steering DACs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Bond pad and ESD protection structure for 0.25μm/0.18μm RF-CMOS.
Proceedings of the ESSCIRC 2003, 2003

2002
A general analysis on the timing jitter in D/A converters.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
AMGIE-A synthesis environment for CMOS analog integrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

High density capacitance structures in submicron CMOS for low power RF application.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

D/A conversion: amplitude and time error mapping optimization.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000
A new faster sequence pair algorithm [circuit layout].
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

On explicit solutions of nonlinear dynamic systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A new efficient method for substrate-aware device-level placement (short paper).
Proceedings of ASP-DAC 2000, 2000

1999
Data processing based on wave propagation.
Int. J. Circuit Theory Appl., 1999

Symbolic analysis of large signals in nonlinear systems.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A new concept for flash AD conversion.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1997
High-level synthesis of analog sensor interface front-ends.
Proceedings of the European Design and Test Conference, 1997

1996
A 3.3 V 625 kHz switched-current multiplier.
IEEE J. Solid State Circuits, 1996

Further extensions to Chua's explicit piecewise linear function descriptions.
Int. J. Circuit Theory Appl., 1996

A low power high performance switched-current multiplier.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
On the restrictions of the sensitivities in single-amplifier biquadratic active filters.
Int. J. Circuit Theory Appl., 1995

Darwin: Analogue circuit synthesis based on genetic algorithms.
Int. J. Circuit Theory Appl., 1995

An analogue module generator for mixed analogue/digital asic design.
Int. J. Circuit Theory Appl., 1995

A New Architecture for a Cyclic Algorithmic D/A Converter.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A High Performance Low Voltage Switched-Current Multiplier.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A flexible topology selection program as part of an analog synthesis system.
Proceedings of the 1995 European Design and Test Conference, 1995

DARWIN: CMOS Opamp Synthesis by Means of a Genetic Algorithm.
Proceedings of the 32st Conference on Design Automation, 1995

1994
A high-performance SI memory cell.
IEEE J. Solid State Circuits, November, 1994

A Methodology for Analog Design Automation in Mixed-Signal ASICs.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
DC Testing of Analog Integrated Circuits with Piecewise Linear Approximation and Interval Analysis.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1991
A flexible hierarchical piecewise linear simulator.
Integr., 1991

Finding all solutions of piecewise linear functions and application to circuit design.
Int. J. Circuit Theory Appl., 1991


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