Dogan Ulus

According to our database, Dogan Ulus authored at least 23 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Elements of Timed Pattern Matching.

Dogan Ulus, Thomas Ferrère, Eugene Asarin, Dejan Nickovic, Oded Maler

ACM Trans. Embed. Comput. Syst., July, 2024

Runtime Verification Containers for Publish/Subscribe Networks.

Ali Mehran, Dogan Ulus

CoRR, 2024

2021

On the Complexity of Timed Pattern Matching.

Eugene Asarin, Thomas Ferrère, Dejan Nickovic, Dogan Ulus

Proceedings of the Formal Modeling and Analysis of Timed Systems, 2021

2020

AMT 2.0: qualitative and quantitative trace analysis with extended signal temporal logic.

Dejan Nickovic, Olivier Lebeltel, Oded Maler, Thomas Ferrère, Dogan Ulus

Int. J. Softw. Tools Technol. Transf., 2020

First-order temporal logic monitoring with BDDs.

Klaus Havelund, Doron Peled, Dogan Ulus

Formal Methods Syst. Des., 2020

2019

Online Monitoring of Metric Temporal Logic using Sequential Networks.

Dogan Ulus

CoRR, 2019

Reactive Control Meets Runtime Verification: A Case Study of Navigation.

Dogan Ulus, Calin Belta

Proceedings of the Runtime Verification - 19th International Conference, 2019

Timescales: A Benchmark Generator for MTL Monitoring Tools.

Dogan Ulus

Proceedings of the Runtime Verification - 19th International Conference, 2019

2018

Pattern Matching with Time : Theory and Applications. (Filtrage par motif temporisé : Théorie et Applications).

Dogan Ulus

PhD thesis, 2018

Sequential Circuits from Regular Expressions Revisited.

Dogan Ulus

CoRR, 2018

Specifying Timed Patterns using Temporal Logic.

Dogan Ulus, Oded Maler

Proceedings of the 21st International Conference on Hybrid Systems: Computation and Control (part of CPS Week), 2018

Embedded software for robotics: challenges and future directions: special session.

Houssam Abbas, Indranil Saha, Yasser Shoukry, Rüdiger Ehlers, Georgios Fainekos, Rajesh Gupta, Rupak Majumdar, Dogan Ulus

Proceedings of the International Conference on Embedded Software, 2018

DejaVu: A Monitoring Tool for First-Order Temporal Logic.

Klaus Havelund, Doron Peled, Dogan Ulus

Proceedings of the 3rd Workshop on Monitoring and Testing of Cyber-Physical Systems, 2018

2017

On the Quantitative Semantics of Regular Expressions over Real-Valued Signals.

Alexey Bakhirkin, Thomas Ferrère, Oded Maler, Dogan Ulus

Proceedings of the Formal Modeling and Analysis of Timed Systems, 2017

Combining the Temporal and Epistemic Dimensions for MTL Monitoring.

Eugene Asarin, Oded Maler, Dejan Nickovic, Dogan Ulus

Proceedings of the Formal Modeling and Analysis of Timed Systems, 2017

Montre: A Tool for Monitoring Timed Regular Expressions.

Dogan Ulus

Proceedings of the Computer Aided Verification - 29th International Conference, 2017

Derivatives of Quantitative Regular Expressions.

Rajeev Alur, Konstantinos Mamouras, Dogan Ulus

Proceedings of the Models, Algorithms, Logics and Tools, 2017

2016

Online Timed Pattern Matching Using Derivatives.

Dogan Ulus, Thomas Ferrère, Eugene Asarin, Oded Maler

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2016

2015

Measuring with Timed Patterns.

Thomas Ferrère, Oded Maler, Dejan Nickovic, Dogan Ulus

Proceedings of the Computer Aided Verification - 27th International Conference, 2015

2014

Timed Pattern Matching.

Dogan Ulus, Thomas Ferrère, Eugene Asarin, Oded Maler

Proceedings of the Formal Modeling and Analysis of Timed Systems, 2014

2013

Analog layer extensions for analog/mixed-signal assertion languages.

Dogan Ulus, Alper Sen, I. Faik Baskaya

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Integrating circuit analyses for assertion-based verification of programmable AMS circuits.

Dogan Ulus, Alper Sen, I. Faik Baskaya

Proceedings of the 2013 Forum on specification and Design Languages, 2013

2012

Using haloes in mixed-signal assertion based verification.

Dogan Ulus, Alper Sen

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012