Doe Hyun Yoon

Orcid: 0000-0002-7019-1354

Affiliations:
  • Google, Mountain View, CA, USA
  • IBM Thomas J. Watson Research Center, Yorktown Heights, USA (former)
  • University of Texas at Austin, Electrical and Computer Engineering Department (former)
  • LG Electronics, DM Research Lab, Kyunggi-Do, Korea (former)


According to our database1, Doe Hyun Yoon authored at least 24 papers between 2004 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2021
The Design Process for Google's Training Chips: TPUv2 and TPUv3.
IEEE Micro, 2021

Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
A domain-specific supercomputer for training deep neural networks.
Commun. ACM, 2020

Google's Training Chips Revealed: TPUv2 and TPUv3.
Proceedings of the IEEE Hot Chips 32 Symposium, 2020

2017
In-Datacenter Performance Analysis of a Tensor Processing Unit.
CoRR, 2017


2014
Hourglass: A Bandwidth-Driven Performance Model for Sorting Algorithms.
Proceedings of the Supercomputing - 29th International Conference, 2014

2013
Containment domains: A scalable, efficient and flexible resilience scheme for exascale systems.
Sci. Program., 2013

Practical nonvolatile multilevel-cell phase change memory.
Proceedings of the International Conference for High Performance Computing, 2013

Kiln: closing the performance gap between systems with and without persistence support.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012
Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism.
IEEE Micro, 2012

MAGE: adaptive granularity and ECC for resilient and power efficient memory systems.
Proceedings of the SC Conference on High Performance Computing Networking, 2012

The dynamic granularity memory system.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

BOOM: Enabling mobile memory based low-power server DIMMs.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Balancing DRAM locality and parallelism in shared memory CMP systems.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Exploring latency-power tradeoffs in deep nonvolatile memory hierarchies.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

2011
Virtualized ECC: Flexible Reliability in Main Memory.
IEEE Micro, 2011

Adaptive granularity memory systems: a tradeoff between storage efficiency and throughput.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

FREE-p: Protecting non-volatile memory against both hard and soft errors.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010
Virtualized and flexible ECC for main memory.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009
Flexible cache error protection using an ECC FIFO.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

Memory mapped ECC: low-cost error protection for last level caches.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

2005
Automatic detection of vibrato in monophonic music.
Pattern Recognit., 2005

2004
Spiral intra macroblock refresh with motion vector restriction for low bit-rate video telephony over a 3G network.
IEEE Trans. Consumer Electron., 2004


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