Dmytro Cherniak
Orcid: 0000-0001-7662-9022
According to our database1,
Dmytro Cherniak
authored at least 28 papers
between 2013 and 2024.
Collaborative distances:
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Bibliography
2024
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.
IEEE J. Solid State Circuits, December, 2023
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner.
IEEE J. Solid State Circuits, March, 2023
A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE J. Solid State Circuits, 2022
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time.
IEEE J. Solid State Circuits, 2022
A 68.6fs<sub>rms</sub>-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2020
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking.
IEEE J. Solid State Circuits, 2020
17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS.
IEEE J. Solid State Circuits, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS : (Invited Paper).
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation.
IEEE J. Solid State Circuits, 2018
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2015
Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters.
Proceedings of the ESSCIRC Conference 2015, 2015
2013
IEEE J. Solid State Circuits, 2013
A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013