Dmitry V. Ponomarev

Proceedings of the SIGSIM-PADS '21: SIGSIM Conference on Principles of Advanced Discrete Simulation, Virtual Event, USA, 31 May, 2021

GVT-Guided Demand-Driven Scheduling in Parallel Discrete Event Simulation.

[BibT_eX]

[DOI]

Proceedings of the ICPP 2021: 50th International Conference on Parallel Processing, Lemont, IL, USA, August 9, 2021

2020

EnsembleHMD: Accurate Hardware Malware Detectors with Specialized Ensemble Classifiers.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2020

Demand-Driven PDES: Exploiting Locality in Simulation Models.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation, 2020

Port or Shim? Stress Testing Application Performance on Intel SGX.

[BibT_eX]

[DOI]

Aisha Hasan

Ryan Riley

Esmaeil Mohammadian Koruyeh

Proceedings of the IEEE International Symposium on Workload Characterization, 2020

2019

LATCH: A Locality-Aware Taint CHecker.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

EA-PLRU: Enclave-Aware Cache Replacement.

[BibT_eX]

[DOI]

Proceedings of the 8th International Workshop on Hardware and Architectural Support for Security and Privacy, 2019

Controlled Asynchronous GVT: Accelerating Parallel Discrete Event Simulation on Many-Core Clusters.

[BibT_eX]

[DOI]

Proceedings of the 48th International Conference on Parallel Processing, 2019

SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation.

[BibT_eX]

[DOI]

Khaled N. Khasawneh

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

SMT-COP: Defeating Side-Channel Attacks on Execution Units in SMT Processors.

[BibT_eX]

[DOI]

Daniel Townley

Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018

Flexible Hardware-Managed Isolated Execution: Architecture, Software Support and Applications.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2018

Performance Implications of Global Virtual Time Algorithms on a Knights Landing Processor.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, 2018

BranchScope: A New Side-Channel Attack on Directional Branch Predictor.

[BibT_eX]

[DOI]

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017

Performance Characterization of Parallel Discrete Event Simulation on Knights Landing Processor.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM SIGSIM Conference on Principles of Advanced Discrete Simulation, 2017

RHMD: evasion-resilient hardware malware detectors.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Hardening extended memory access control schemes with self-verified address spaces.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks.

[BibT_eX]

[DOI]

Mehmet Kayaalp

Khaled N. Khasawneh

Hodjat Asghari Esfeden

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Hardware-Based Malware Detection Using Low-Level Architectural Features.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Understanding and Mitigating Covert Channels Through Branch Predictors.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2016

Rethinking Memory Permissions for Protection Against Cross-Layer Attacks.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2016

Jump over ASLR: Attacking branch predictors to bypass ASLR.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

A high-resolution side-channel attack on last-level cache.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Covert Channels through Random Number Generator: Mechanisms, Capacity Estimation and Mitigations.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, 2016

2015

AIR: Application-Level Interference Resilience for PDES on Multicore Systems.

[BibT_eX]

[DOI]

ACM Trans. Model. Comput. Simul., 2015

Signature-Based Protection from Code Reuse Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Ensemble Learning for Low-Level Hardware-Supported Malware Detection.

[BibT_eX]

[DOI]

Proceedings of the Research in Attacks, Intrusions, and Defenses, 2015

Covert channels through branch predictors: a feasibility study.

[BibT_eX]

[DOI]

Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015

Controlled Contention: Balancing Contention and Reservation in Multicore Application Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium, 2015

Malware-aware processors: A framework for efficient online malware detection.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014

Parallel Discrete Event Simulation for Multi-Core Systems: Analysis and Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2014

SIFT: Low-Complexity Energy-Efficient Information Flow Tracking on SMT Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Efficiently Securing Systems from Code Reuse Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Exploring many-core architecture design space for parallel discrete event simulation.

[BibT_eX]

[DOI]

Proceedings of the SIGSIM Principles of Advanced Discrete Simulation, 2014

Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution.

[BibT_eX]

[DOI]

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Dynamic associative caches: Reducing dynamic energy of first level caches.

[BibT_eX]

[DOI]

Karthikeyan Dayalan

Meltem Ozsoy

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

A Non-Inclusive Memory Permissions architecture for protection against cross-layer attacks.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

Instruction Scheduling in Microprocessors.

[BibT_eX]

[DOI]

Gürhan Küçük

Isa Ahmet Güney

Proceedings of the Automated Scheduling and Planning - From Theory to Practice, 2013

Can PDES scale in environments with heterogeneous delays?

[BibT_eX]

[DOI]

Proceedings of the SIGSIM Principles of Advanced Discrete Simulation, 2013

Interference resilient PDES on multi-core systems: towards proportional slowdown.

[BibT_eX]

[DOI]

Proceedings of the SIGSIM Principles of Advanced Discrete Simulation, 2013

PowerVisor: A Toolset for Visualizing Energy Consumption and Heat Dissipation Processes in Modern Processor Architectures.

[BibT_eX]

[DOI]

Alexey Baranov

Peter Panfilov

Proceedings of the Parallel Computing Technologies - 12th International Conference, 2013

SCRAP: Architecture for signature-based protection from Code Reuse Attacks.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2012

Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2012

Performance Analysis of a Multithreaded PDES Simulator on Multicore Clusters.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE/SCS Workshop on Principles of Advanced and Distributed Simulation, 2012

Characterizing and Understanding PDES Behavior on Tilera Architecture.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE/SCS Workshop on Principles of Advanced and Distributed Simulation, 2012

Partitioning on Dynamic Behavior for Parallel Discrete Event Simulation.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE/SCS Workshop on Principles of Advanced and Distributed Simulation, 2012

Branch regulation: Low-overhead protection from code reuse attacks.

[BibT_eX]

[DOI]

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Optimization of Parallel Discrete Event Simulator for Multi-core Systems.

[BibT_eX]

[DOI]

Deepak Jagtap

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

Tensor model of IMS network.

[BibT_eX]

[DOI]

Proceedings of the 4th International Congress on Ultra Modern Telecommunications and Control Systems, 2012

2011

CacheVisor: A Toolset for Visualizing Shared Caches in Multicore and Multithreaded Processors.

[BibT_eX]

[DOI]

Peter Panfilov

Proceedings of the Parallel Computing Technologies - 11th International Conference, 2011

TPM-SIM: a framework for performance evaluation of trusted platform modules.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

SIFT: a low-overhead dynamic information flow tracking architecture for SMT processors.

[BibT_eX]

[DOI]

Proceedings of the 8th Conference on Computing Frontiers, 2011

Mathematical limits of parallel computation for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Customized architectures for faster route finding in GPS-based navigation systems.

[BibT_eX]

[DOI]

Patrick H. Madden

Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

A Predictive Model for Cache-Based Side Channels in Multicore and Multithreaded Microprocessors.

[BibT_eX]

[DOI]

Leonid Domnitser

Proceedings of the Computer Network Security, 2010

A co-processor approach for accelerating data-structure intensive algorithms.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Computer Design, 2010

Performance Evaluation of PDES on Multi-core Clusters.

[BibT_eX]

[DOI]

Proceedings of the DS-RT '10 Proceedings of the 2010 IEEE/ACM 14th International Symposium on Distributed Simulation and Real Time Applications, 2010

2009

MPTLsim: a cycle-accurate, full-system simulator for x86-64 multicore architectures with coherent caches.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2009

Energy-efficient renaming with register versioning.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

[BibT_eX]

[DOI]

Hui Zeng

Proceedings of the ICPP 2009, 2009

MPTLsim: a simulator for X86 multicore processors.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Selective Writeback: Reducing Register File Pressure and Energy Consumption.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

Reducing register pressure in SMT processors through L2-miss-driven early register release.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2008

Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch Signatures.

[BibT_eX]

[DOI]

Balaji Vijayn

Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

Aggressive Scheduling and Speculation in Multithreaded Architectures: Is it Worth its Salt?

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

Hiding Communication Delays in Clustered Microarchitectures.

[BibT_eX]

[DOI]

Robert J. LaDuca

Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

Two-Level Reorder Buffers: Accelerating Memory-Bound Applications on SMT Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Parallel Processing, 2008

2007

Exploiting Operand Availability for Efficient Simultaneous Multithreading.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

An L2-miss-driven early register deallocation for SMT processors.

[BibT_eX]

[DOI]

Proceedings of the 21th Annual International Conference on Supercomputing, 2007

2006

Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Early Register Deallocation Mechanisms Using Checkpointed Register Files.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Instruction packing: Toward fast and energy-efficient instruction scheduling.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2006

Selective writeback: exploiting transient values for energy-efficiency and performance.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Balancing ILP and TLP in SMT Architectures through Out-of-Order Instruction Dispatch.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Parallel Processing (ICPP 2006), 2006

Address-Value Decoupling for Early Register Deallocation.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Parallel Processing (ICPP 2006), 2006

Efficient instruction schedulers for SMT processors.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 2006

Adaptive reorder buffers for SMT processors.

[BibT_eX]

[DOI]

Deniz Balkan

Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006

2005

Instruction packing: reducing power and delay of the dynamic scheduling logic.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Power-Efficient Wakeup Tag Broadcast.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Instruction Recirculation: Eliminating Counting Logic in Wakeup-Free Schedulers.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005

Non-uniform Instruction Scheduling.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005

2004

Energy Efficient Comparators for Superscalar Datapaths.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

Isolating Short-Lived Operands for Energy Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

Complexity-Effective Reorder Buffer Designs for Superscalar Processors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization.

[BibT_eX]

[DOI]

Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004

[BibT_eX]

[DOI]

Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Increasing Processor Performance Through Early Register Release.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003

Energy-efficient issue queue design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Energy Efficient Register Renaming.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

Power efficient comparators for long arguments in superscalar processors.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Reducing reorder buffer complexity through selective operand caching.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Distributed Reorder Buffer Schemes for Low Power.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Reducing Datapath Energy through the Isolation of Short-Lived Operands.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

2002

Energy-Efficient Design of the Reorder Buffer.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Low-complexity reorder buffer architecture.

[BibT_eX]

[DOI]

Proceedings of the 16th international conference on Supercomputing, 2002

A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

2001

Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources.

[BibT_eX]

[DOI]

Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Energy: efficient instruction dispatch buffer design for superscalar processors.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Optimal Polling for Latency-Throughput Tradeoffs in Queue-Based Network Interfaces for Clusters.

[BibT_eX]

[DOI]

Evgeny Saksonov

Proceedings of the Euro-Par 2001: Parallel Processing, 2001

1998

A comparative study of some network subsystem organizations.

[BibT_eX]

[DOI]