Dmitry Osipov

Orcid: 0000-0003-1729-3092

Affiliations:
  • University of Bremen, Institute of Electrodynamics and Microelectronics, Germany
  • National Research Nuclear University MEPHI, Moscow, Russia


According to our database1, Dmitry Osipov authored at least 18 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
Method to Reduce the Number of Metastability Errors in Asynchronous SAR ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

2020
An Energy Efficient SAR ADC Architecture with DAC Separation.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

2019
Compact Extended Industrial Range CMOS Current References.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Two-Step Pipeline SAR ADC with passive Charge Sharing between Cascades.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

Multi-step capacitor switching scheme for low-power SAR ADC.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

First Order Fully Passive Noise-Shaping SAR ADC Architecture with NTF Zero close to One.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

2018
Flying-Capacitor Bottom-Plate Sampling Scheme for Low-Power High-Resolution SAR ADCs.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Energy-Efficient Architecture for Neural Spikes Acquisition.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017
Temperature-Compensated β-Multiplier Current Reference Circuit.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

8-Channel Neural Stimulation ASIC for Epidural Visual Cortex Stimulation.
J. Circuits Syst. Comput., 2017

Two-step monotonic switching scheme for low-power SAR ADCs.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Compact first order temperature-compensated CMOS current reference.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Simulation-based design procedure for sub 1V CMOS current reference.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Current driver with read-out HV protection for neural stimulation.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

8 Channel neural stimulation ASIC for epidural visual cortex stimulation with on board 90 ppm/°C current reference.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
A new current stimulator architecture for visual cortex stimulation.
Proceedings of the Nordic Circuits and Systems Conference, 2015

A novel HV-switch scheme with gate-source overvoltage protection for bidirectional neural interfaces.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2012
A Low-Power 9-bit Pipelined CMOS ADC with Amplifier and Comparator Sharing Technique
CoRR, 2012


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