Dmitry Evtyushkin

Orcid: 0000-0002-0549-0438

According to our database1, Dmitry Evtyushkin authored at least 16 papers between 2011 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
STBPU: A Reasonably Secure Branch Prediction Unit.
Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022

2021
STBPU: A Reasonably Safe Branch Predictor Unit.
CoRR, 2021

Computing with time: microarchitectural weird machines.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
Exploring Branch Predictors for Constructing Transient Execution Trojans.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
A Systematic Evaluation of Transient Execution Attacks and Defenses.
Proceedings of the 28th USENIX Security Symposium, 2019

SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Flexible Hardware-Managed Isolated Execution: Architecture, Software Support and Applications.
IEEE Trans. Dependable Secur. Comput., 2018

BranchScope: A New Side-Channel Attack on Directional Branch Predictor.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Hardening extended memory access control schemes with self-verified address spaces.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

On the Detection of Kernel-Level Rootkits Using Hardware Performance Counters.
Proceedings of the 2017 ACM on Asia Conference on Computer and Communications Security, 2017

2016
Understanding and Mitigating Covert Channels Through Branch Predictors.
ACM Trans. Archit. Code Optim., 2016

Jump over ASLR: Attacking branch predictors to bypass ASLR.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Covert Channels through Random Number Generator: Mechanisms, Capacity Estimation and Mitigations.
Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, 2016

2015
Covert channels through branch predictors: a feasibility study.
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015

2014
Iso-X: A Flexible Architecture for Hardware-Managed Isolated Execution.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2011
CacheVisor: A Toolset for Visualizing Shared Caches in Multicore and Multithreaded Processors.
Proceedings of the Parallel Computing Technologies - 11th International Conference, 2011


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