Dmitry Burlyaev

Orcid: 0000-0001-8685-6923

According to our database1, Dmitry Burlyaev authored at least 7 papers between 2014 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Bibliography

2018
A Static Analysis for the Minimization of Voters in Fault-Tolerant Circuits.
Leibniz Trans. Embed. Syst., 2018

2015
Design, Optimization, and Formal Verification of Circuit Fault-Tolerance Techniques. (Conception, optimisation, et vérification formelle de techniques de tolérance aux fautes pour circuits).
PhD thesis, 2015

Automatic Time-Redundancy Transformation for Fault-Tolerant Circuits.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Formal Verification of Automatic Circuit Transformations for Fault-Tolerance.
Proceedings of the Formal Methods in Computer-Aided Design, 2015

Time-redundancy transformations for adaptive fault-tolerant circuits.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014
System fault-tolerance analysis of COTS-based satellite on-board computers.
Microelectron. J., 2014

Verification-guided voter minimization in triple-modular redundant circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014


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