Dmitri Mihhailov

According to our database, Dmitri Mihhailov authored at least 16 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis.

Sergei Devadze, Christine Elizabeth Nielsen, Dmitri Mihhailov, Peeter Ellervee

Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024

2022

HLS-based Optimization of Tau Triggering Algorithm for LHC: a case study.

Natalia Cherezova, Dmitri Mihhailov, Sergei Devadze, Artur Jutman

CoRR, 2022

2013

Implementation of address-based data sorting on different FPGA platforms.

Dmitri Mihhailov, Alexander Sudnitson, Valery Sklyarov, Iouliia Skliarova

Proceedings of the East-West Design & Test Symposium, 2013

Address-based data processing over N-ary trees.

Valery Sklyarov, Iouliia Skliarova, Margus Kruus, Dmitri Mihhailov, Alexander Sudnitson

Proceedings of Eurocon 2013, 2013

Optimization of address-based data sorting unit with external memory support.

Dmitri Mihhailov, Artjem Rjabov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson

Proceedings of the Computer Systems and Technologies, 2013

2012

Performance evaluation for FPGA-based processing of tree-like structures.

Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

EEG Analyzer prototype based on FPGA.

Maksim Jenihhin, Maksim Gorev, Vadim Pesonen, Dmitri Mihhailov, Peeter Ellervee, Hiie Hinrikus, Maie Bachmann, Jaanus Lass

Proceedings of the 7th International Symposium on Image and Signal Processing and Analysis, 2011

Implementation in FPGA of Address-Based Data Sorting.

Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

High-performance hardware accelerators for sorting and managing priorities.

Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Recursion and hierarchy in digital design and prototyping: a case study.

Dmitri Mihhailov, Margus Kruus, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson

Proceedings of the 12th International Conference on Computer Systems and Technologies, 2011

2010

Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules.

Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Parallel FPGA-Based Implementation of Recursive Sorting Algorithms.

Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Application-specific hardware accelerator for implementing recursive sorting algorithms.

Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson

Proceedings of the International Conference on Field-Programmable Technology, 2010

Advanced topics of FSM design using FPGA educational boards and web-based tools.

Alexander Sudnitson, Dmitri Mihhailov, Margus Kruus

Proceedings of the 2010 East-West Design & Test Symposium, 2010

2009

FSM decomposition with application to FPGA synthesis.

Alexander Sudnitson, Dmitri Mihhailov, Margus Kruus, Konstantin Tarletski

Proceedings of the 2009 International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, 2009

2008

FPGA platform based digital design education.

Dmitri Mihhailov, Margus Kruus, Alexander Sudnitson

Proceedings of the 9th International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing, 2008