Djordje Jevdjic

Orcid: 0000-0002-3341-9364

According to our database1, Djordje Jevdjic authored at least 26 papers between 2012 and 2024.

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Bibliography

2024
AttentionStore: Cost-effective Attention Reuse across Multi-turn Conversations in Large Language Model Serving.
CoRR, 2024

numaPTE: Managing Page-Tables and TLBs on NUMA Systems.
CoRR, 2024

Scalable and Effective Page-table and TLB management on NUMA Systems.
Proceedings of the 2024 USENIX Annual Technical Conference, 2024

Cost-Efficient Large Language Model Serving for Multi-turn Conversations with CachedAttention.
Proceedings of the 2024 USENIX Annual Technical Conference, 2024

DNA Storage Toolkit: A Modular End-to-End DNA Data Storage Codec and Simulator.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2024

2023
Efficiently Enabling Block Semantics and Data Updates in DNA Storage.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

2022
Efficiently Supporting Hierarchy and Data Updates in DNA Storage.
CoRR, 2022

Simulating Noisy Channels in DNA Storage.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

OS-level Implications of Using DRAM Caches in Memory Disaggregation.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

Managing reliability skew in DNA storage.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2021
Exploiting Errors for Efficiency: A Survey from Circuits to Applications.
ACM Comput. Surv., 2021

2020
SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators.
CoRR, 2020

2018
Exploiting Errors for Efficiency: A Survey from Circuits to Algorithms.
CoRR, 2018

2017
Fat Caches for Scale-Out Servers.
IEEE Micro, 2017

Clustering Billions of Reads for DNA Data Storage.
Proceedings of the Advances in Neural Information Processing Systems 30: Annual Conference on Neural Information Processing Systems 2017, 2017

Approximate Storage of Compressed and Encrypted Videos.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

Near-Memory Address Translation.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2015
Multi-Gigabyte On-Chip DRAM Caches for Servers.
PhD thesis, 2015

2014
A Case for Specialized Processors for Scale-Out Workloads.
IEEE Micro, 2014

Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2013
Die-stacked DRAM caches for servers: hit ratio, latency, or bandwidth? have it all with footprint cache.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

From A to E: analyzing TPC's OLTP benchmarks: the obsolete, the ubiquitous, the unexplored.
Proceedings of the Joint 2013 EDBT/ICDT Conferences, 2013

2012
Quantifying the Mismatch between Emerging Scale-Out Applications and Modern Processors.
ACM Trans. Comput. Syst., 2012

Scale-out processors.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Thermal characterization of cloud workloads on a power-efficient server-on-chip.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Clearing the clouds: a study of emerging scale-out workloads on modern hardware.
Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012


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