Divyanshu Divyanshu

Orcid: 0000-0002-0010-4788

According to our database¹, Divyanshu Divyanshu authored at least 8 papers between 2022 and 2023.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

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PhD thesis

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Bibliography

2023

FSM Inspired Unconventional Hardware Watermark Using Field-Assisted SOT-MTJ.

[BibT_eX]

[DOI]

IEEE Access, 2023

Cybersecurity Regulation of Smart Mobility Hardware Systems: Case Assessment for Spin-Based MTJ Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Smart Mobility, 2023

Finite-State-Machine inspired Hardware Watermark using Spin-Orbit Torque operated MTJ.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

Logic Locking Using Emerging 2T/3T Magnetic Tunnel Junctions for Hardware Security.

[BibT_eX]

[DOI]

IEEE Access, 2022

Physically Unclonable Function Using GSHE Driven SOT Assisted p-MTJ for Next Generation Hardware Security Applications.

[BibT_eX]

[DOI]

IEEE Access, 2022

Physically Unclonable Function using GSHE driven SOT assisted MTJ for next Generation Hardware Security Applications.

[BibT_eX]

[DOI]

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

Modeling of Sneaky Hardware Trojan Using Spin-orbit Torque Assisted Magnetic Tunnel Junction for High Speed Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

Logic Locking for Hardware Security Using Voltage-Gated Spin-orbit Torque Magnetic Tunnel Junction.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

Divyanshu Divyanshu

Timeline

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Bibliography

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