Divya Duvvuri

According to our database1, Divya Duvvuri authored at least 7 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2023
A -102dBm Sensitivity, 2.2μA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2020
30.1 A Temperature-Robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X-Band.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2016
Design and analysis of a current mode integrated CTLE with charge mode adaptation.
Microelectron. J., 2016

An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A new hybrid circuit topology for simultaneous bidirectional signaling over on-chip interconnects.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2014
100-Mbps transceiver for enhanced MIL-STD-1553.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014


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