Dirk Stroobandt

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

Balancing Intra-Die and Inter-Die Placement Optimization in 2.5D FPGA Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

Exploring Large Language Models for Verilog Hardware Design Generation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

LiquidMD: Optimizing Inter-die and Intra-die placement for 2.5D FPGA Architectures.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2024

2023

FPGA-Based Hyperspectral Lossy Compressor With Adaptive Distortion Feature for Unexpected Scenarios.

[BibT_eX]

[DOI]

IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2023

Modularity Driven Parallel Placement Algorithm for 2.5D FPGA Architectures.

[BibT_eX]

[DOI]

Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, 2023

On the Interconnection Complexity vs Size Trade-off in Circuit Graphs.

[BibT_eX]

[DOI]

Marieke Louage

Muhammad Mazher Iqbal

Proceedings of the ACM International Workshop on System-Level Interconnect Pathfinding, 2023

2022

RWRoute: An Open-source Timing-driven Router for Commercial FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2022

Multi-Die Heterogeneous FPGAs: How Balanced Should Netlist Partitioning be?

[BibT_eX]

[DOI]

Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022

2021

RWRoute: An Open-source Timing-driven Router for Commercial FPGAs.

[BibT_eX]

[DOI]

Dataset, November, 2021

cREAtIve: reconfigurable embedded artificial intelligence.

[BibT_eX]

[DOI]

Proceedings of the CF '21: Computing Frontiers Conference, 2021

2020

Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2020

In-Circuit Debugging with Dynamic Reconfiguration of FPGA Interconnects.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2020

3D NoC emulation model on a single FPGA.

[BibT_eX]

[DOI]

Jonathan D'Hoore

Proceedings of the SLIP '20: System-Level Interconnect, 2020

On the Exploration of Connection-aware Partitioning for Parallel FPGA Routing.

[BibT_eX]

[DOI]

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019

Reco-Pi: A reconfigurable Cryptoprocessor for π-Cipher.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2019

An Integrated on-Silicon Verification Method for FPGA Overlays.

[BibT_eX]

[DOI]

J. Electron. Test., 2019

A New Adaptation of Particle Swarm Optimization Applied to Modern FPGA Placement.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Synthesis, 2019

MODA-PSO: Towards Fast Hard Block Legalization for Analytical FPGA Placement.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

CRoute: A Fast High-Quality Timing-Driven Connection-Based FPGA Router.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018

Data Reuse Buffer Synthesis Using the Polyhedral Model.

[BibT_eX]

[DOI]

Wim Meeus

IEEE Trans. Very Large Scale Integr. Syst., 2018

How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Traffic-aware reconfigurable architecture for fault-tolerant 2D mesh NoCs.

[BibT_eX]

[DOI]

SIGBED Rev., 2018

Abacus turn model-based routing for NoC interconnects with switch or link failures.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2018

3D MAX: A Maximally Adaptive Routing Method for VC-less 3D Mesh-based Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 11th International Workshop on Network on Chip Architectures, 2018

Superimposed in-circuit debugging for self-healing FPGA overlays.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Introduction to RAW 2018.

[BibT_eX]

[DOI]

Diana Goehringer

Ken Eguro

Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Hierarchical Force-Based Block Spreading for Analytical FPGA Placement.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Reconfigurable FPGA Implementation of the AVC Quantiser and De-quantiser Blocks.

[BibT_eX]

[DOI]

Vijaykumar Guddad

Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2018

2017

Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications.

[BibT_eX]

[DOI]

CoRR, 2017

Adaptive and reconfigurable bubble routing technique for 2D Torus interconnection networks.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project.

[BibT_eX]

[DOI]

Marco Domenico Santambrogio

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

SICTA: A superimposed in-circuit fault tolerant architecture for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Dynamically Reconfigurable Architecture for Fault-Tolerant 2D Networks-on-Chip.

[BibT_eX]

[DOI]

Azarakhsh Jalalvand

Proceedings of the 26th International Conference on Computer Communication and Networks, 2017

Liquid: High quality scalable placement for large heterogeneous FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2017

A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration.

[BibT_eX]

[DOI]

Ana Lucia Varbanescu

Proceedings of the International Conference on Field Programmable Technology, 2017

An open reconfigurable research platform as stepping stone to exascale high-performance computing.

[BibT_eX]

[DOI]

Gabriel Figueiredo

Andreas Brokalakis

Michael Hübner

Tobias Becker

Alex J. W. Thom

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Adaptive state space representations enabling reliable and robust decision-making in asynchronous drives for mechatronic applications.

[BibT_eX]

[DOI]

Arne De Keyser

Guillaume Crevecoeur

Proceedings of the IEEE International Conference on Advanced Intelligent Mechatronics, 2017

2016

How to Efficiently Reconfigure Tunable Lookup Tables for Dynamic Circuit Specialization.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2016

MiCAP-Pro: a high speed custom reconfiguration controller for Dynamic Circuit Specialization.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2016

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures.

[BibT_eX]

[DOI]

Ana Lucia Varbanescu

Wayne Luk

Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Online reconfigurable routing method for handling link failures in NoC-based MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Efficient Hardware Debugging Using Parameterized FPGA Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

A 16-Bit Reconfigurable Encryption Processor for p-Cipher.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Runtime-quality tradeoff in partitioning based multithreaded packing.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Liquid: Fast placement prototyping through steepest gradient descent movement.

[BibT_eX]

[DOI]

Seppe Lenders

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

On the Impact of Replacing Low-Speed Configuration Buses on FPGAs with the Chip's Internal Configuration Infrastructure.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2015

Identification of Dynamic Circuit Specialization Opportunities in RTL Code.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2015

TCONMAP: Technology Mapping for Parameterised FPGA Configurations.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

Enabling FPGA routing configuration sharing in dynamic partial reconfiguration.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2015

The Hamiltonian-based odd-even turn model for maximally adaptive routing in 2D mesh networks-on-chip.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2015

MiCAP: a custom reconfiguration controller for dynamic circuit specialization.

[BibT_eX]

[DOI]

Kizheppatt Vipin

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Power measurements and analysis for dynamic circuit specialization.

[BibT_eX]

[DOI]

Robin Bonamy

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Design and exploration of routing methods for NoC-based multicore systems.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

ParaFPGA15: Exploring threads and trends in programmable hardware.

[BibT_eX]

[DOI]

Proceedings of the Parallel Computing: On the Road to Exascale, 2015

Design of TSV-Sharing Topologies for Cost-Effective 3D Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 8th International Workshop on Network on Chip Architectures, 2015

Test set generation almost for free using a run-time FPGA reconfiguration technique.

[BibT_eX]

[DOI]

Proceedings of the 16th Latin-American Test Symposium, 2015

Estimating circuit delays in FPGAs after technology mapping.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Logic Gates in the routing network of FPGAs (Abstract Only).

[BibT_eX]

[DOI]

Berg Severens

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Avoiding transitional effects in dynamic circuit specialisation on FPGAs.

[BibT_eX]

[DOI]

Karel Heyse

Proceedings of the 52nd Annual Design Automation Conference, 2015

EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing.

[BibT_eX]

[DOI]

Ana Lucia Varbanescu

George Charitopoulos

Xinyu Niu

Wayne Luk

Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

Hamiltonian Path Strategy for Deadlock-Free and Adaptive Routing in Diametrical 2D Mesh NoCs.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE/ACM International Symposium on Cluster, 2015

2014

TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Hard versus Soft Software Defined Radio.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Adaptive multicast routing method for 3D mesh-based Networks-on-Chip.

[BibT_eX]

[DOI]

Azarakhsh Jalalvand

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Improving reconfiguration speed for dynamic circuit specialization using placement constraints.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Parameterised FPGA reconfigurations for efficient test set generation.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Data path analysis for dynamic circuit specialisation.

[BibT_eX]

[DOI]

Tom Davidson

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Characterizing Traffic Locality in 3D NoC-Based CMPs Using a Path-Based Partitioning Method.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual Symposium on High-Performance Interconnects, 2014

Reducing the overhead of dynamic partial reconfiguration for multi-mode circuits.

[BibT_eX]

[DOI]

Brahim Al Farisi

Karel Heyse

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Performance Evaluation of Dynamic Circuit Specialization on Xilinx FPGAs.

[BibT_eX]

[DOI]

Proceedings of the FPGA World Conference 2014, 2014

Automating data reuse in High-Level Synthesis.

[BibT_eX]

[DOI]

Wim Meeus

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Improving hamiltonian-based routing methods for on-chip networks: A turn model approach.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Effective Reconfigurable Design: The FASTER Approach.

[BibT_eX]

[DOI]

Georgi Nedeltchev Gaydadjiev

Tobias Becker

Andreas Brokalakis

Wayne Luk

Ioannis Papaefstathiou

Danilo Pau

Oliver Pell

Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA's Configuration Infrastructure.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013

How to efficiently implement dynamic circuit specialization systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Training energy-based models for time-series imputation.

[BibT_eX]

[DOI]

Philemon Brakel

J. Mach. Learn. Res., 2013

The Hamiltonian-based odd-even turn model for adaptive routing in interconnection networks.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Making Communication a First-Class Citizen in Multicore Partitioning.

[BibT_eX]

[DOI]

Ruxandra-Marina Florea

Proceedings of the 21st Euromicro International Conference on Parallel, 2013

ParaFPGA 2013: Harnessing Programs, Power and Performance in Parallel FPGA applications.

[BibT_eX]

[DOI]

Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013

A novel tool flow for increased routing configuration similarity in multi-mode circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Bidirectional truncated recurrent neural networks for efficient speech denoising.

[BibT_eX]

[DOI]

Philemon Brakel

Proceedings of the 14th Annual Conference of the International Speech Communication Association, 2013

Towards balanced traffic distribution in NoCs using a highly adaptive path-based routing algorithm.

[BibT_eX]

[DOI]

Proceedings of the International Conference on High Performance Computing & Simulation, 2013

The FASTER vision for designing dynamically reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of 2013 International Conference on IC Design & Technology, 2013

A connection-based router for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Staticroute: A novel router for the Dynamic Partial Reconfiguration of FPGAS.

[BibT_eX]

[DOI]

Brahim Al Farisi

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

An automatic tool flow for the combined implementation of multi-mode circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2012

An overview of today's high-level synthesis tools.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2012

Smart technologies for effective reconfiguration: The FASTER approach.

[BibT_eX]

[DOI]

Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Maximizing the reuse of routing resources in a reconfiguration-aware connection router.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Mapping logic to reconfigurable FPGA routing.

[BibT_eX]

[DOI]

Karel Heyse

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Automatically exploiting regularity in applications to reduce reconfiguration memory requirements.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.

[BibT_eX]

[DOI]

Ioannis Papaefstathiou

Oliver Pell

M. Robart

Tim Todman

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

A Connection Router for the Dynamic Reconfiguration of FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

Dynamic data folding with parameterizable FPGA configurations.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2011

Constructing Application-Specific Memory Hierarchies on FPGAs.

[BibT_eX]

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2011

Automatic detection of epileptic seizures on the intra-cranial electroencephalogram of rats using reservoir computing.

[BibT_eX]

[DOI]

Artif. Intell. Medicine, 2011

RecoNoC: A reconfigurable network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

A Dynamically Reconfigurable Pattern Matcher for Regular Expressions on FPGA.

[BibT_eX]

[DOI]

Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

ParaFPGA 2011 - High Performance Computing with Multiple FPGAs: Design Methodology and Applications.

[BibT_eX]

[DOI]

Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010

SLIP: 10 years ago and 10 years from now.

[BibT_eX]

[DOI]

Patrick Groeneveld

Louis Scheffer

Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Run-Time Reconfiguration for Automatic Hardware/Software Partitioning.

[BibT_eX]

[DOI]

Tom Davidson

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

PinComm: Characterizing Intra-application Communication for the Many-Core Era.

[BibT_eX]

[DOI]

Narasinga Rao Miniskar

Roel Wuyts

Francky Catthoor

Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010

Efficiently Generating FPGA Configurations through a Stack Machine.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

A Parallel for Loop Memory Template for a High Level Synthesis Compiler.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Towards a Tighter Integration of Generated and Custom-Made Hardware.

[BibT_eX]

[DOI]

Wim Meeus

Proceedings of the Reconfigurable Computing: Architectures, 2010

TROUTE: A Reconfigurability-Aware FPGA Router.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2010

2009

Efficient memory management for hardware accelerated Java Virtual Machines.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Teaching skills and concepts for embedded systems design.

[BibT_eX]

[DOI]

SIGBED Rev., 2009

Accelerating Event-Driven Simulation of Spiking Neurons with Multiple Synaptic Time Constants.

[BibT_eX]

[DOI]

Neural Comput., 2009

Pruning and regularization in reservoir computing.

[BibT_eX]

[DOI]

Neurocomputing, 2009

Using method interception for hardware/software co-development.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2009

Applying Parameterizable Dynamic Configurations to Sequence Alignment.

[BibT_eX]

[DOI]

Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009

ParaFPGA: Parallel Computing with Flexible Hardware.

[BibT_eX]

[DOI]

Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009

Towards a more efficient run-time FPGA configuration generation.

[BibT_eX]

[DOI]

Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009

Optimizing the FPGA Memory Design for a Sobel Edge Detector.

[BibT_eX]

Craig Moore

Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Automatically mapping applications to a self-reconfiguring platform.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Strategies for dynamic memory allocation in hybrid architectures.

[BibT_eX]

[DOI]

Proceedings of the 6th Conference on Computing Frontiers, 2009

2008

Predicting the performance of reconfigurable optical interconnects in distributed shared-memory systems.

[BibT_eX]

[DOI]

Photonic Netw. Commun., 2008

Event detection and localization for small mobile robots using reservoir computing.

[BibT_eX]

[DOI]

Eric A. Antonelo

Neural Networks, 2008

Improving reservoirs using intrinsic plasticity.

[BibT_eX]

[DOI]

Neurocomputing, 2008

Modeling multiple autonomous robot behaviors and behavior switching with a single reservoir computing network.

[BibT_eX]

[DOI]

Eric Aislan Antonelo

Proceedings of the IEEE International Conference on Systems, 2008

Rent's rule and parallel programs: characterizing network traffic behavior.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Imitation Learning of an Intelligent Navigation System for Mobile Robots Using Reservoir Computing.

[BibT_eX]

[DOI]

Eric A. Antonelo

Proceedings of the 10th Brazilian Symposium on Neural Networks (SBRN 2008), 2008

Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Reconfigurability-Aware Structural Mapping for LUT-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Band-pass Reservoir Computing.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2008

Efficient measurement of data flow enabling communication-aware parallelisation.

[BibT_eX]

[DOI]

Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, 2008

Mobile robot control in the road sign problem using Reservoir Computing networks.

[BibT_eX]

[DOI]

Eric A. Antonelo

Proceedings of the 2008 IEEE International Conference on Robotics and Automation, 2008

Real-Time Epileptic Seizure Detection on Intra-cranial Rat Data Using Reservoir Computing.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neuro-Information Processing, 15th International Conference, 2008

Stable Output Feedback in Reservoir Computing Using Ridge Regression.

[BibT_eX]

[DOI]

Francis Wyffels

Proceedings of the Artificial Neural Networks, 2008

Automatic generation of run-time parameterizable configurations.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

Pruning and Regularisation in Reservoir Computing: a First Insight.

[BibT_eX]

[DOI]

Xavier Dutoit

Hendrik Van Brussel

Marnix Nuttin

Proceedings of the 16th European Symposium on Artificial Neural Networks, 2008

Java and the Power of Multi-Core Processing.

[BibT_eX]

[DOI]

Proceedings of the Second International Conference on Complex, 2008

2007

Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect.

[BibT_eX]

[DOI]

Ian O'Connor

Faress Tissafi-Drissi

IEEE Trans. Very Large Scale Integr. Syst., 2007

Scalable, Wavelet-Based Video: From Server to Hardware-Accelerated Client.

[BibT_eX]

[DOI]

IEEE Trans. Multim., 2007

Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations.

[BibT_eX]

[DOI]

Kristof Beyls

Mark Christiaens

Trans. High Perform. Embed. Archit. Compil., 2007

An experimental unification of reservoir computing methods.

[BibT_eX]

[DOI]

Neural Networks, 2007

Special issue on System-Level Interconnect Prediction.

[BibT_eX]

[DOI]

Igor L. Markov

Louis Scheffer

Integr., 2007

Predicting reconfigurable interconnect performance in distributed shared-memory systems.

[BibT_eX]

[DOI]

Integr., 2007

FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2007

The Energy Scalability of Wavelet-Based, Scalable Video Decoding.

[BibT_eX]

[DOI]

Hendrik Eeckhaut

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Parallel Computing with FPGAs - Concepts and Applications.

[BibT_eX]

Proceedings of the Parallel Computing: Architectures, 2007

Mobility of Data in Distributed Hybrid Computing Systems.

[BibT_eX]

[DOI]

Philippe Faes

Mark Christiaens

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Event Detection and Localization in Mobile Robot Navigation Using Reservoir Computing.

[BibT_eX]

[DOI]

Proceedings of the Artificial Neural Networks, 2007

Improving External Memory Access for Avalon Systems on Programmable Chips..

[BibT_eX]

[DOI]

Hendrik Eeckhaut

Mark Christiaens

Proceedings of the FPL 2007, 2007

A Method for Fast Hardware Specialization at run-time.

[BibT_eX]

[DOI]

Proceedings of the FPL 2007, 2007

Adapting reservoir states to get Gaussian distributions.

[BibT_eX]

[DOI]

David Verstraeten

Proceedings of the 15th European Symposium on Artificial Neural Networks, 2007

Energy Scalability and the RESUME Scalable Video Codec.

[BibT_eX]

[DOI]

Proceedings of the Power-aware Computing Systems, 21.01. - 26.01.2007, 2007

2006

Scalable hardware accelerator for comparing DNA and protein sequences.

[BibT_eX]

[DOI]

Proceedings of the 1st International Conference on Scalable Information Systems, 2006

Reservoir-based techniques for speech recognition.

[BibT_eX]

[DOI]

David Verstraeten

Proceedings of the International Joint Conference on Neural Networks, 2006

Accelerating Event Based Simulation for Multi-synapse Spiking Neural Networks.

[BibT_eX]

[DOI]

Michiel D'Haene

Proceedings of the Artificial Neural Networks, 2006

Optimizing the critical loop in the H.264/AVC CABAC decoder.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2005

Isolated word recognition with the Liquid State Machine: a case study.

[BibT_eX]

[DOI]

Inf. Process. Lett., 2005

Prediction model for evaluation of reconfigurable interconnects in distributed shared-memory systems.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

Towards reconfigurable optical networks on chip.

[BibT_eX]

Faress Tissafi-Drissi

Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

FPGA-Aware Garbage Collection in Java.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Isolated word recognition using a Liquid State Machine.

[BibT_eX]

[DOI]

David Verstraeten

Proceedings of the 13th European Symposium on Artificial Neural Networks, 2005

A Hardware-Friendly Wavelet Entropy Codec for Scalable Video.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2004

Toward the accurate prediction of placement wire length distributions in VLSI circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

2003

A priori wire length distribution models with multiterminal nets.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Improved a priori interconnect predictions and technology extrapolation in the GTX system.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Fast estimation of the partitioning rent characteristic using a recursive partitioning model.

[BibT_eX]

[DOI]

Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

Hardware implementation of an EAN-13 bar code decoder.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Efficient Microprocessor Design Space Exploration through Statistical Simulatio.

[BibT_eX]

[DOI]

Lieven Eeckhout

Koenraad De Bosschere

Proceedings of the Proceedings 36th Annual Simulation Symposium (ANSS-36 2003), Orlando, Florida, USA, March 30, 2003

2002

Guest editorial - system-level interconnect prediction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Toward better wireload models in the presence of obstacles.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

A probabilistic approach to clock cycle prediction.

[BibT_eX]

[DOI]

Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Getting more out of Donath's hierarchical model for interconnect prediction.

[BibT_eX]

[DOI]

Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002

AQUASUN: adaptive window query processing in CAD applications for physical design and verification.

[BibT_eX]

[DOI]

Michiel De Wilde

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001

A stochastic model for the interconnection topology of digital circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Toward accurate models of achievable routing.

[BibT_eX]

[DOI]

Andrew B. Kahng

Stefanus Mantik

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

On partitioning vs. placement rent properties.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

A priori system-level interconnect prediction: Rent's rule and wire length distribution models.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Multi-terminal nets do change conventional wire length distribution models.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

On rent's rule for rectangular regions.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

2000

The interpretation and application of Rent's rule.

[BibT_eX]

[DOI]

Phillip Christie

IEEE Trans. Very Large Scale Integr. Syst., 2000

Generating synthetic benchmark circuits for evaluating CAD tools.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Efficient representation of interconnection length distributions using generating polynomials.

[BibT_eX]

[DOI]

Herwig Van Marck

Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000

Wiring layer assignments with consistent stage delays.

[BibT_eX]

[DOI]

Andrew B. Kahng

Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000

Requirements for models of achievable routing.

[BibT_eX]

[DOI]

Andrew B. Kahng

Stefanus Mantik

Proceedings of the 2000 International Symposium on Physical Design, 2000

On synthetic benchmark generation methods.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

GTX: the MARCO GSRC technology extrapolation system.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle.

[BibT_eX]

[DOI]

VLSI Design, 1999

Generating new benchmark designs using a multi-terminal net model.

[BibT_eX]

[DOI]

Jo Depreitere

Integr., 1999

Towards synthetic benchmark circuits for evaluating timing-driven CAD tools.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Physical Design, 1999

On an Efficient Method for Estimating the Interconnection Complexity of Designs and on the Existence of Region III in Rent's Rule.

[BibT_eX]

[DOI]

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998

On the Characterization of Multi-Point Nets in Electronic Designs.

[BibT_eX]

[DOI]

Fadi J. Kurdahi

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

A Quantitative Study of the Benefits of Area-I/O in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1996

An Accurate Interconnection Length Estimation for Computer Logic.

[BibT_eX]

[DOI]

Herwig Van Marck

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Hierarchical Test Generation with Built-In Fault Diagnosis.

[BibT_eX]

[DOI]