Dirk Pfaff
Orcid: 0000-0002-9658-5765
According to our database1,
Dirk Pfaff
authored at least 8 papers
between 1999 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
IEEE J. Solid State Circuits, January, 2025
2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2020
A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2020
2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2008
A 1.8W 115Gb/s Serial Link for Fully Buffered DIMM with 2.1ns Pass-Through Latency in 90nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2000
IEEE J. Solid State Circuits, 2000
1999
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999