Dipankar Sarkar

According to our database, Dipankar Sarkar authored at least 56 papers between 1989 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Translation validation of coloured Petri net models of programs on integers.

Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal, Holger Giese

Acta Informatica, 2022

2019

Verification of parallelising transformations of KPN models.

Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal

IET Cyper-Phys. Syst.: Theory & Appl., 2019

Equivalence checking of Petri net models of programs using static and dynamic cut-points.

Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal

Acta Informatica, 2019

SamaTulyataOne: A Path Based Equivalence Checker.

Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal

Proceedings of the 12th Innovations on Software Engineering Conference (formerly known as India Software Engineering Conference), 2019

2017

Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers.

Kunal Banerjee, Dipankar Sarkar, Chittaranjan Mandal

IEEE Trans. Software Eng., 2017

Synchronization Validation for Cross-Thread Dependences in Parallel Programs.

Sudakshina Dutta, Dipankar Sarkar, Arvind Rawat

Int. J. Parallel Program., 2017

Deriving bisimulation relations from path based equivalence checkers.

Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal

Formal Aspects Comput., 2017

An Equivalence Checking Framework for Array-Intensive Programs.

Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar

Proceedings of the Automated Technology for Verification and Analysis, 2017

SamaTulyata: An Efficient Path Based Equivalence Checking Tool.

Soumyadip Bandyopadhyay, Santonu Sarkar, Dipankar Sarkar, Chittaranjan A. Mandal

Proceedings of the Automated Technology for Verification and Analysis, 2017

2016

A Path Construction Algorithm for Translation Validation Using PRES+ Models.

Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal, Kunal Banerjee, Krishnam Raju Duddu

Parallel Process. Lett., 2016

Translation validation of loop and arithmetic transformations in the presence of recurrences.

Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar

Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, 2016

An efficient path based equivalence checking for Petri net based models of programs.

Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal

Proceedings of the 9th India Software Engineering Conference, 2016

Validation of Loop Parallelization and Loop Vectorization Transformations.

Sudakshina Dutta, Dipankar Sarkar, Arvind Rawat, Kulwant Singh

Proceedings of the ENASE 2016, 2016

An Enhanced Equivalence Checking Method to Handle Bugs in Programs with Recurrences.

Sudakshina Dutta, Dipankar Sarkar

Proceedings of the ENASE 2016, 2016

2015

A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs.

Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar

Proceedings of the 15th IEEE International Working Conference on Source Code Analysis and Manipulation, 2015

Translation Validation of Transformations of Embedded System Specifications Using Equivalence Checking.

Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Validating SPARK: High Level Synthesis Compiler.

Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Path-based Equivalence Checking Method for Petri Net based Models of Programs.

Soumyadip Bandyopadhyay, Dipankar Sarkar, Kunal Banerjee, Chittaranjan A. Mandal

Proceedings of the ICSOFT-EA 2015, 2015

Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs.

Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal

Proceedings of the 37th IEEE/ACM International Conference on Software Engineering, 2015

2014

Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs.

Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Verification of Code Motion Techniques Using Value Propagation.

Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers.

Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

2013

Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors.

Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A Kleene Algebra of Tagged System Actors for Reasoning about Heterogeneous Embedded Systems.

Soumyajit Dey, Dipankar Sarkar, Anupam Basu

IEEE Trans. Computers, 2013

Verification of KPN Level Transformations.

Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012

Formal verification of code motion techniques using data-flow-driven equivalence checking.

Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar

ACM Trans. Design Autom. Electr. Syst., 2012

Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker.

Soumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques.

Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal

Proceedings of the International Symposium on Electronic System Design, 2012

2011

A Kleene Algebra of Tagged System Actors.

Soumyajit Dey, Dipankar Sarkar, Anupam Basu

IEEE Embed. Syst. Lett., 2011

Verification of Register Transfer Level Low Power Transformations.

Chandan Karfa, Chitta Mandal, Dipankar Sarkar

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Equivalence Checking of Array-Intensive Programs.

Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chitta Mandal

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010

Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits.

Chandan Karfa, Dipankar Sarkar, Chitta Mandal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A Tag Machine Based Performance Evaluation Method for Job-Shop Schedules.

Soumyajit Dey, Dipankar Sarkar, Anupam Basu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Diagnosability of delay-deadline failures in fair real time discrete event models.

Santosh Biswas, Dipankar Sarkar, Siddhartha Mukhopadhyay

Int. J. Syst. Sci., 2010

Fairness of Transitions in Diagnosability of Discrete Event Systems.

Santosh Biswas, Dipankar Sarkar, Siddhartha Mukhopadhyay, Amit Patra

Discret. Event Dyn. Syst., 2010

Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques.

Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2008

An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.

Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Unified Technique for on-Line Testing of Digital Circuits: Delay and Stuck-at Fault Models.

Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar

J. Circuits Syst. Comput., 2008

2007

Fault diagnosis in discrete time hybrid systems - A case study.

Prodip Bhowal, Dipankar Sarkar, Siddhartha Mukhopadhyay, Anupam Basu

Inf. Sci., 2007

Register Sharing Verification During Data-Path Synthesis.

Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade

Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Hand-in-hand verification of high-level synthesis.

Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

Verification of Scheduling in High-level Synthesis.

Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

A Formal Verification Method of Scheduling in High-level Synthesis.

Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Concurrent Testing of Digital Circuits for Advanced Fault Models.

Santosh Biswas, Siddhartha Mukhopadhyay, P. Patra, Dipankar Sarkar

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Fairness of transitions in diagnosability analysis of hybrid systems.

Santosh Biswas, Chandan Karfa, Himani Kanwar, Dipankar Sarkar, Siddhartha Mukhopadhyay, Amit Patra

Proceedings of the American Control Conference, 2006

2005

On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models.

Santosh Biswas, P. Srikanth, R. Jha, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Model checking on state transition diagram.

Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2002

Register Transfer Operation Analysis during Data Path Verification.

Dipankar Sarkar

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2000

Status Condition Analysis during Data Path Verification of Sequential Circuits.

Dipankar Sarkar

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1997

Verification of Tempura specification of sequential circuits.

M. Hira, Dipankar Sarkar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Inductive Verification of Sequential Circuits with a Datapath.

I. Chakrabarti, Dipankar Sarkar, Arun K. Majumdar

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1995

Identification of Inductive Properties during Verification of Synchronous Sequential Circuits.

I. Chakrabarti, Dipankar Sarkar, Arun K. Majumdar

J. Autom. Reason., 1995

1994

Mechanical Identification of Inductive Properties During Verification of Finite State Machines.

I. Chakrabarti, Dipankar Sarkar

Proceedings of the Seventh International Conference on VLSI Design, 1994

1989

A Theorem Prover for Verifying Iterative Programs Over Integers.

Dipankar Sarkar, S. C. De Sarkar

IEEE Trans. Software Eng., 1989

A Set of Inference Rules for Quantified Formula Handling and Array Handling in Verification of Programs Over Integers.

Dipankar Sarkar, S. C. De Sarkar

IEEE Trans. Software Eng., 1989

Some Inference Rules for Integer Arithmetic for Verification of Flowchart Programs on Integers.

Dipankar Sarkar, S. C. De Sarkar

IEEE Trans. Software Eng., 1989