Dipankar Pal

According to our database, Dipankar Pal authored at least 21 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Strong-ARM Dynamic Latch Comparators: Design and Analyses on CAD Platform.

Kasi Bandla, Dipankar Pal

CoRR, 2024

Deploying Artificial Intelligence in Design Verification to Accelerate IP/SoC Sign-off with Zero Escape.

Surajit Bhattacherjee, Daksh Shah, Dipankar Pal

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

IP Transformation Initiatives to Generate Scalable Functional Verification Collaterals for Smart Reusability and Reduced Effort for Sign-off.

Surajit Bhattacherjee, Dipankar Pal

Proceedings of the International Conference on Computing, Networking and Communications, 2023

2022

Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier.

Aloke Saha, Rakesh Kumar Singh, Dipankar Pal

Microelectron. J., 2022

2021

Efficient ternary comparator on CMOS technology.

Aloke Saha, Narendra Deo Singh, Dipankar Pal

Microelectron. J., 2021

Novel All-Pass Section for High-Performance Signal Processing Using CMOS DCCII.

Taaha Nizam, Vallabhuni Vijay, Avireni Srinivasulu, Dipankar Pal

Proceedings of the IEEE Region 10 Conference, 2021

2020

ASIC Implementation of High-Speed Adaptive Recursive Karatsuba Multiplier with Square-Root-Carry-Select-Adder.

Akhilesh G. Naik, Debarshi Deka, Dipankar Pal

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

2019

RF Harvesting System for Low-Power Applications Using FinFETs.

T. Nagateja, Avireni Srinivasulu, Dipankar Pal

Proceedings of the IEEE International Conference on Consumer Electronics, 2019

2018

Secured and Imperceptible Data Transmission Through Digital Audio Signal with Reduced Internal Noise.

Dipankar Pal, Nabin Ghoshal

Wirel. Pers. Commun., 2018

Modified Time-Based Current Mode ADC.

Suparno Pal, Dipankar Pal

Proceedings of the TENCON 2018, 2018

Delay estimation, chip-power analyses and comparison of single-level and multi-level recursive vedic algorithm with conventional algorithms for digital multiplier.

Dipankar Pal, Akhilesh G. Naik

Proceedings of the 2018 International Conference on IC Design & Technology, 2018

2017

CCII+ based dual square-and-triangular waveform generator.

Avireni Srinivasulu, Dipankar Pal

Proceedings of the 9th International Conference on Electronics, 2017

2014

A Low Power 8-Bit Asynchronous SAR ADC Design Using Charge Scaling DAC.

Anush Bekal, Manish Goswami, B. R. Singh, Dipankar Pal

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

2013

Low-power 6-GHz wave-pipelined 8b x 8b multiplier.

Aloke Saha, Dipankar Pal, Mahesh Chandra

IET Circuits Devices Syst., 2013

2010

A wide-input linear range sub-threshold transconductor for sub-Hz filtering.

Chutham Sawigun, Dipankar Pal, Andreas Demosthenous

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Current Conveyor-Based Square/Triangular Waveform Generators With Improved Linearity.

Dipankar Pal, Avireni Srinivasulu, Basab Bijoy Pal, Andreas Demosthenous, B. N. Das

IEEE Trans. Instrum. Meas., 2009

Novel Current-mode Waveform Generator with Independent Frequency and Amplitude Control.

Dipankar Pal, Avireni Srinivasulu, Manish Goswami

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2007

A low-power CMOS analog voltage buffer using compact adaptive biasing.

Chutham Sawigun, Jirayuth Mahattanakul, Andreas Demosthenous, Dipankar Pal

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

A low-voltage, low-power, high-linearity cmos four-quadrant analog multiplier.

Chutham Sawigun, Andreas Demosthenous, Dipankar Pal

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2005

Two preamplifiers for non-invasive on-chip recording of neural-signals.

Robert Rieger, Dipankar Pal, John Taylor, Peter J. Langlois

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

10-channel very low noise ENG amplifier system using CMOS technology.

Robert Rieger, Dipankar Pal, John Taylor, Chris Clarke, Peter J. Langlois, Nick Donaldson

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005