Ding-Yong Hong
Orcid: 0000-0002-7649-7581
According to our database1,
Ding-Yong Hong
authored at least 36 papers
between 2005 and 2024.
Collaborative distances:
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Bibliography
2024
Effective Compression of Language Models by Combining Pruning and Knowledge Distillation.
Proceedings of the 48th IEEE Annual Computers, Software, and Applications Conference, 2024
2023
Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023
Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023
Accelerate Inference of CNN Models on CPU via Column Combining Based on Simulated Annealing.
Proceedings of the Eleventh International Symposium on Computing and Networking, CANDAR 2023, Matsue, Japan, November 28, 2023
2022
ACM Trans. Archit. Code Optim., 2022
Int. J. Netw. Comput., 2022
Proceedings of the 28th IEEE International Conference on Parallel and Distributed Systems, 2022
Proceedings of the 28th IEEE International Conference on Parallel and Distributed Systems, 2022
Proceedings of the 46th IEEE Annual Computers, Software, and Applications Conferenc, 2022
Proceedings of the IEEE International Conference on Big Data, 2022
2021
Proceedings of the 35th IEEE International Parallel and Distributed Processing Symposium, 2021
Proceedings of the Ninth International Symposium on Computing and Networking, 2021
Proceedings of the 2021 IEEE International Conference on Big Data (Big Data), 2021
2019
ACM Trans. Archit. Code Optim., 2019
ACM Trans. Archit. Code Optim., 2019
Optimizing data permutations in structured loads/stores translation and SIMD register mapping for a cross-ISA dynamic binary translator.
J. Syst. Archit., 2019
Proceedings of the 48th International Conference on Parallel Processing, 2019
2018
ACM Trans. Embed. Comput. Syst., 2018
Softw. Pract. Exp., 2018
Proceedings of the 2018 Conference on Research in Adaptive and Convergent Systems, 2018
Proceedings of the International Conference on Compilers, 2018
2017
Dynamic translation of structured Loads/Stores and register mapping for architectures with SIMD extensions.
Proceedings of the 18th ACM SIGPLAN/SIGBED Conference on Languages, 2017
Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
2016
ACM Trans. Archit. Code Optim., 2016
Proceedings of the 22nd IEEE International Conference on Parallel and Distributed Systems, 2016
2015
J. Syst. Archit., 2015
Proceedings of the 21st IEEE International Conference on Parallel and Distributed Systems, 2015
2014
IEEE Trans. Parallel Distributed Syst., 2014
DBILL: an efficient and retargetable dynamic binary instrumentation framework using llvm backend.
Proceedings of the 10th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2014
2013
Improving dynamic binary optimization through early-exit guided code region formation.
Proceedings of the ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments (co-located with ASPLOS 2013), 2013
2012
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012
2011
LnQ: Building High Performance Dynamic Binary Translators with Existing Compiler Backends.
Proceedings of the International Conference on Parallel Processing, 2011
2010
Proceedings of the 12th UKSim, 2010
2009
Proceedings of the 2009 Spring Simulation Multiconference, SpringSim 2009, 2009
2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
2005
Proceedings of the 8th International Symposium on Parallel Architectures, 2005