Dinesh Ramanathan

According to our database1, Dinesh Ramanathan authored at least 8 papers between 1998 and 2002.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

1998
1999
2000
2001
2002
0
1
2
3
4
5
1
1
4
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2002
An analysis of system level power management algorithms and theireffects on latency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2000
Interfacing Hardware and Software Using C++ Class Libraries.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Latency Effects of System Level Power Management Algorithms.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

System Level Online Power Management Algorithms.
Proceedings of the 2000 Design, 2000

Timing driven co-design of networked embedded systems.
Proceedings of ASP-DAC 2000, 2000

1999
Timing-driven HW/SW codesign based on task structuring and process timing simulation.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
A timing-driven design and validation methodology for embedded real-time systems.
ACM Trans. Design Autom. Electr. Syst., 1998

Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems.
Proceedings of the 35th Conference on Design Automation, 1998


  Loading...