Dinesh Prasad

Orcid: 0000-0003-3677-7455

According to our database1, Dinesh Prasad authored at least 9 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Impact of Variability on Novel Transistor Configurations in Adder Circuits at 7nm FinFET Technology.
J. Circuits Syst. Comput., September, 2024

Effect of ambipolarity suppression in PNPN TFET with dopant segregated Schottky-drain technique.
Microelectron. J., 2024

Novel III-V inverted T-channel TFET with dual-gate impact on line tunneling, with and without negative capacitance.
Microelectron. J., 2024

An energy and area-efficient spike frequency adaptable LIF neuron for spiking neural networks.
Comput. Electr. Eng., 2024

2023
Temperature Sensitivity and Reliability Study of Symmetrical U-Shaped Gate Line TFET: RF/Analog and Linearity Performance Analysis.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

2021
Simulation study and comparative analysis of proposed novel hybrid DG-TFET with conventional TFETs structures for improved performance.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2017
Novel Ms⁁2 type FDNR simulation configuration with electronic control and grounded capacitances.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
Novel active PID controller employing VDTA.
Proceedings of the 2016 IEEE International Symposium on Signal Processing and Information Technology, 2016

2014
Voltage-Mode New Universal Biquad Filter Configuration Using a Single VDIBA.
Circuits Syst. Signal Process., 2014


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