Dinesh Kushwaha

According to our database, Dinesh Kushwaha authored at least 15 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network.

Dinesh Kushwaha, Jaya Kumar Abotula, Rajat Kohli, Jwalant Mishra, Sudeb Dasgupta, Anand Bulusu

IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

An Energy-Efficient SRAM-Based Charge Domain Compute In-Memory Architecture.

Anmol Singla, Dinesh Kushwaha, Gulyawar Aman, Shubhradin Chakraborty, Abhishek Goel, Anand Bulusu, Sudeb Dasgupta

Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024

Variation-Aware Design Methodology for SRAM-Based Multi-Bit Analog Compute-in-Memory Architecture.

Dinesh Kushwaha, Rajiv V. Joshi, Anand Bulusu, Sudeb Dasgupta

Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024

An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture.

Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Jainendra Singh, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network.

Aditya Sharma, Vatsal Dixit, Dinesh Kushwaha, Nitanshu Chauhan, Vishal Kumar Saxena, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology.

Dinesh Kushwaha, Ashish Joshi, Abhishek Goel, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network.

Subhradip Chakraborty, Dinesh Kushwaha, Abhishek Goel, Anmol Singla, Anand Bulusu, Sudeb Dasgupta

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin.

Dinesh Kushwaha, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN.

Subhradip Chakraborty, Dinesh Kushwaha, Anand Bulusu, Sudeb Dasgupta

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology.

Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application.

Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN.

Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing.

Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture.

Neha Gupta, Ashish Joshi, Dinesh Kushwaha, Vinod Menezes, Rashmi Sachan, Sudeb Dasgupta, Anand Bulusu

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2016

A 415 nW, 0.8 V, voltage reference circuit using MOSFETs in saturation and sub-threshold regions.

Dinesh Kushwaha, D. K. Mishra

Proceedings of the 11th International Conference on Industrial and Information Systems, 2016