Dinesh D. Gaitonde

According to our database, Dinesh D. Gaitonde authored at least 4 papers between 1993 and 1996.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1996

Fatal Fault Probability Prediction for Array Based Designs.

Dinesh D. Gaitonde, Wojciech Maly, D. M. H. Walker

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995

Accurate yield estimation of circuits with redundancy.

Dinesh D. Gaitonde, D. M. H. Walker, Wojciech Maly

Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1993

Estimation of reject ratio in testing of combinatorial circuits.

Dinesh D. Gaitonde, Jitendra Khare, D. M. H. Walker, Wojciech P. Maly

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

Test quality and yield analysis using the DEFAM defect to fault mapper.

Dinesh D. Gaitonde, Duncan M. Hank Walker

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993