Dimitris Kaseridis

According to our database1, Dimitris Kaseridis authored at least 10 papers between 2009 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2014
Cache Friendliness-Aware Managementof Shared Last-Level Caches for HighPerformance Multi-Core Systems.
IEEE Trans. Computers, 2014

2011
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue.
IEEE Micro, 2011

Modeling program resource demand using inherent program characteristics.
Proceedings of the SIGMETRICS 2011, 2011

Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

The virtual write queue: coordinating DRAM and last-level cache policies.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

System-level max power (SYMPO): a systematic approach for escalating system-level power consumption using synthetic benchmarks.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Bank-aware Dynamic Cache Partitioning for Multicore Architectures.
Proceedings of the ICPP 2009, 2009


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