Dimitris Bakalis

A. Anastasiou

Circuits Syst. Signal Process., 2015

2013

RNS assisted image filtering and edge detection.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Digital Signal Processing, 2013

On the design of modulo 2n-1 cubing units.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Reverse converters for RNSs with diminished-one encoded channels.

[BibT_eX]

[DOI]

Proceedings of Eurocon 2013, 2013

Modulo 2n-2 arithmetic units.

[BibT_eX]

[DOI]

Proceedings of Eurocon 2013, 2013

2012

CSD-RNS-based Single Constant Multipliers.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2012

Area-time efficient multi-modulus adders and their applications.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2012

SUT-RNS Residue-to-Binary Converters Design.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

Efficient modulo 2n±1 squarers.

[BibT_eX]

[DOI]

Anastasia Spyrou

Integr., 2011

On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2011

On the use of double-LSB and signed-LSB encodings for RNS.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Digital Signal Processing, 2011

Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion.

[BibT_eX]

[DOI]

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010

On Implementing Efficient Modulo 2n + 1 Arithmetic Components.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2010

Fast modulo 2n+1 multi-operand adders and residue generators.

[BibT_eX]

[DOI]

Costas Efstathiou

Integr., 2010

SUT-RNS Forward and Reverse Converters.

[BibT_eX]

[DOI]

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Area-Efficient Multi-moduli Squarers for RNS.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

Efficient partial scan cell gating for low-power scan-based testing.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Novel modulo 2n+1 subtractors.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Digital Signal Processing, 2009

Efficient architectures for modulo 2n-1 squares.

[BibT_eX]

[DOI]

Anastasia Spyrou

Proceedings of the 16th International Conference on Digital Signal Processing, 2009

Combined SD-RNS Constant Multiplication.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

Efficient modulo 2n + 1 multi-operand adders.

[BibT_eX]

[DOI]

Costas Efstathiou

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2006

A core generator for arithmetic cores and testing structures with a network interface.

[BibT_eX]

[DOI]

Kostas Adaos

Dimitrios Lymperopoulos

J. Syst. Archit., 2006

2004

An Efficient Test Vector Ordering Method for Low Power Testing.

[BibT_eX]

[DOI]

Maciej Bellos

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Scan Cell Ordering for Low Power BIST.

[BibT_eX]

[DOI]

Maciej Bellos

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Low Power Testing by Test Vector Ordering with Vector Repetition.

[BibT_eX]

[DOI]

Maciej Bellos

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2002

A new built-in TPG method for circuits with random patternresistant faults.

[BibT_eX]

[DOI]

Spyros Tragoudas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation.

[BibT_eX]

[DOI]

J. Syst. Archit., 2002

On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST.

[BibT_eX]

[DOI]

Emmanouil Kalligeros

J. Electron. Test., 2002

An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST.

[BibT_eX]

[DOI]

Emmanouil Kalligeros

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register.

[BibT_eX]

[DOI]

Giorgos Dimitrakopoulos

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

2001

Δομές ενσωματωμένου αυτοελέγχου για ψηφιακά κυκλώματα πολύ μεγάλης κλίμακας ολοκλήρωσης

[BibT_eX]

[DOI]

PhD thesis, 2001

Low Power Built-In Self-Test Schemes for Array and Booth Multipliers.

[BibT_eX]

[DOI]

G. Ph. Alexiou

VLSI Design, 2001

EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores.

[BibT_eX]

[DOI]

Dimitrios Lymperopoulos

Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001

On Accumulator-Based Bit-Serial Test Response Compaction Schemes.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

On the Design of Self-Testing Checkers for Modified Berger Codes.

[BibT_eX]

[DOI]

Stanislaw J. Piestrak

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A New Reseeding Technique for LFSR-Based Test Pattern Generation.

[BibT_eX]

[DOI]

Emmanouil Kalligeros

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A novel reseeding technique for accumulator-based test pattern generation.

[BibT_eX]

[DOI]

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000

Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Low Power BIST for Wallace Tree-Based Fast Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

1999

Low Power Dissipation in BIST Schemes for Modified Booth Multipliers.

[BibT_eX]

[DOI]